TIDUFD2 May   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Terminology
    2. 1.2 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Input Capacitors Selection
      2. 2.2.2 DC Side
      3. 2.2.3 AC Side
    3. 2.3 Highlighted Products
      1. 2.3.1 TMDSCNCD28P55X - controlCARD Evaluation Module
        1. 2.3.1.1 Hardware Features
        2. 2.3.1.2 Software Features
      2. 2.3.2 LMG2100R026 - 100V, 53A GaN Half-Bridge Power Stage
      3. 2.3.3 LMG365xR035 - 650V 35mΩ GaN FET With Integrated Driver and Protection
      4. 2.3.4 TMCS1123 - Precision 250kHz Hall-Effect Current Sensor With Reinforced Isolation
      5. 2.3.5 TMCS1133 - Precision 1MHz Hall-Effect Current Sensor With Reinforced Isolation
      6. 2.3.6 INA185 - 26V, 350kHz, Bidirectional, High-Precision Current Sense Amplifier
      7. 2.3.7 LM5164 – 100V Input, 1A Synchronous Buck DC-DC Converter With Ultra-Low IQ
      8. 2.3.8 ISO6762 – General-Purpose Six-Channel Reinforced Digital Isolators With Robust EMC
  9. 3System Design Theory
    1. 3.1 Isolation for Solar Inverters
    2. 3.2 Topology Overview
    3. 3.3 Control Theory
      1. 3.3.1 Single and Extended Phase Shift Modulation Technique
      2. 3.3.2 Zero Voltage Switching and Circulating Current
      3. 3.3.3 Optimized Control Method
      4. 3.3.4 Dead-Time Compensation
      5. 3.3.5 Frequency Modulation
      6. 3.3.6 Controller Block Diagram
    4. 3.4 MPPT and Input Voltage Ripple
  10. 4Hardware, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
    2. 4.2 Test Setup
      1. 4.2.1 Board Check
      2. 4.2.2 DC-DC Tests
      3. 4.2.3 DC-AC Tests
    3. 4.3 Test Results
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author

3.3.4 Dead-Time Compensation

As previous sections in this design guide illustrate, the dead time plays an important role in ZVS realization. Unfortunately ZVS cannot be realized in the full range of voltage gains and loads, especially at the mode change point. When the converter loses ZVS for one of the legs, the effective phase shift changes causing distortion in the output current waveform.

The reason for the phase shift change is as follows: real applications employ switches with inherent dead time to prevent shoot-through and allow current to discharge in the switches. When Zero Voltage Switching (ZVS) is enabled, both the primary and secondary sides initiate the changes immediately upon the complementary switch being turned off. In cases of good ZVS, a new voltage is reached before the dead time expires.

A hard switch keeps the voltage unchanged until a turn-on event forces the voltage to a new level at the end of dead time.

TIDA-010954 Phase Shift Variations Figure 3-15 Phase Shift Variations

Dead-time effects alter the effective phase shift. Implementation of ZVS across different legs introduces varying changes in D1 and D2. Table 3-1 shows the compensation values for different legs.

Table 3-1 Dead-Time Compensation Values
ZVS REALIZATION COMPENSATION FOR D1 COMPENSATION FOR D2
Primary lead –DTDC +DTDC/2
Primary lag +DTDC +DTDC/2
Secondary 0 –DTAC

To understand the ZVS realization, the controller calculates switch currents for all legs. Table 3-2 shows equations for turn-off current calculation.

Table 3-2 Equations for Turn-Off Currents
MODE II MODE III
Primary lead
N × V D C × D 1 - 1 2 + V G × D 1 2 - D 2 + 0.25 2 × F S W × L K
N × V D C × D 1 - 1 2 + V G × 0.25 2 × F S W × L K
Primary lag
N × V D C × - D 1 + 1 2 + V G × D 1 2 + D 2 - 0.25 2 × F S W × L K
N × V D C × - D 1 + 1 2 + V G × D 1 2 + D 2 - 0.25 2 × F S W × L K
Secondary
N × V D C × 2 × D 2 - 1 2 + V G × 0.25 2 × F S W × L K
N × V D C × D 1 - 1 2 + V G × - D 1 2 + D 2 + 0.25 2 × F S W × L K

If the calculated turn-off current is negative, then compensation can be applied with these switches. However, in real applications just positive current is not enough to realize ZVS, because the switches require some significant current to discharge COSS within the dead time. If this current is not enough, there can be partial soft switching. So the compensation value in Table 3-1 needs to be linearized. In the linear compensation approach, additional linear coefficient KCOMP is calculated in equation Equation 9 and applied to dead-time compensation values in Table 3-1.

Equation 9. K C O M P = m i n 1 ,   I Z V S - I s I Z V S

where

  • IS is the switch current
  • IZVS is the desired current for full ZVS

The coefficient determines how hard the switching event is for this leg. Zeroing out the coefficient indicates that the turn-off current in this leg is sufficient to fully realize ZVS. However, when the coefficient is 1, the switching event is fully hard and the controller must apply full compensation effort to D1 and D2 values. The system designer chooses the desired IZVS after characterizing the system. Notably, IZVS can differ for primary and secondary sides because COSS varies.

Deployment of the proposed compensation measures significantly reduces current spikes in the grid and improves THD for the converter.