TIDUFD2 Design guide

TIDUFD2 May 2025

3.3.3 Optimized Control Method

In the case of the fixed frequency DAB converter with half-bridge, the designer has two values of control: internal and fundamental phase shift. The control algorithm needs to be designed to deliver reference current to the grid, thus fundamental phase shift is typically dependent on output current requirement and internal phase shift. The internal phase shift has some degree of freedom to optimize ZVS behavior. The optimized control method for this reference design is considered in [2].

In the optimized control method, the extended phase shift (EPS) is implemented with two modes of operation. In mode III, the positive pulse of V_P is fully located inside the positive V_S pulse. In mode II, the positive pulse of V_P overlaps with both the positive and negative V_S pulse. Mode I has a positive pulse for V_P, is fully located inside the negative V_S pulse. Mode I has significant circulating current and is not considered.

Figure 3-11 Mode III of Operation

Mode III has lower RMS current and is preferred for light loads, while mode II is used for high loads.

Figure 3-12 Mode II of Operation

The range of D1 is the internal phase shift with a range of 0 to 0.5 where 0 means the maximum primary side pulse width and 0.5 means minimum primary side pulse width. D2 is the fundamental phase shift with range –0.25 to +0.25, where positive values means power flow from the DC side to AC side.

By definition of the operation modes, Equation 1 shows the only possible mode III operation.

Equation 1.

D 1 > 2 \times |D 2|

Equation 2 defines the normalized output current.

Equation 2.

I_{N} = \frac{N \times V_{D C}}{4 \times f_{s w} \times L_{K}}

where

V_DC is the DC side voltage
N = transformer secondary to primary turns ratio
Fs = switching frequency
Lk = inductor value

The fundamental phase shift D2 is used to regulate output current, thus D2 is predefined by current reference and D1.

Equation 3.

\{\begin{matrix} {D 2}_{I I} = \frac{1 - \sqrt{1 - 4 \times M - 4 \times {D 1}^{2}}}{4} \times s g n (I_{R E F}) \\ {D 2}_{I I I} = \frac{M}{2 \times (1 - 2 \times D 1)} \times s g n (I_{R E F}) \end{matrix}

where

M = | I_REF/I_N | is the current transmission ratio

The internal phase shift is calculated with ZVS requirements. The control method defines ZVS requirements as zero current trajectories for the primary side lagging arm in Equation 4. The primary side leading arm can always realize ZVS, so the primary side is not considered.

Equation 4.

\{\begin{matrix} {D 1}_{I I, P R I} = \frac{(2 - m) - \sqrt{{(2 + m)}^{2} - (2 \times m^{2} - (2 \times m^{2} + 4 \times m + 4) \times (1 + m^{2} \times (M - 0.25)))}}{2 \times m^{2} + 4 \times m + 4} \\ {D 1}_{I I I, P R I} = 0.25 - 0.5 \times \sqrt{|\frac{m \times M}{1 - 0.5 \times m}|} \end{matrix}

where

m = | V_AC |/N × V_DC is the voltage gain

If the requirement in Equation 5 is satisfied, the converter can operate in mode III to realize ZVS. In this case D1_III,PRI is used as the primary side requirement. Otherwise, the converter needs to operate in mode II and D1_II,PRI is used. If the control algorithm keeps D1 < D1_PRI then primary side lagging arm can realize ZVS.

Equation 5.

{D 1}_{P R I} = \{\begin{matrix} {D 1}_{I I, P R I}, M \geq {D 1}_{I I I, P R I} \times (1 - 2 \times {D 1}_{I I I, P R I}) \\ {D 1}_{I I I, P R I}, o t h e r w i s e \end{matrix}

Equation 6 defines the ZVS requirement for secondary-side switches.

Equation 6.

\{\begin{matrix} {D 1}_{I I, S E C} = \sqrt{m a x \{0, 0.25 - M - \frac{m^{2}}{16}\}} \\ {D 1}_{I I I, S E C} = 0.5 - 0.25 \times m \end{matrix}

Equation 7.

{D 1}_{S E C} = \{\begin{matrix} {D 1}_{I I, S E C}, M \geq {D 1}_{I I I, S E C} \times (1 - 2 \times {D 1}_{I I I, S E C}) \\ {D 1}_{I I I, S E C}, o t h e r w i s e \end{matrix}

Similarly, if the requirement in Equation 7 is satisfied the D1_III,SEC value is used as secondary side requirement, otherwise the D1_II,SEC value is used. If the control algorithm keeps D1 > D1_SEC, then the primary side lag arm can realize ZVS.

Figure 3-13 and Figure 3-14 show the calculated ZVS requirement curves within a grid cycle.

TIDA-010954 ZVS Curves Over AC Half
Wave at High Load

Figure 3-13 ZVS Curves Over AC Half Wave at High Load

TIDA-010954 ZVS Curves Over AC Half
Wave at Medium Load

Figure 3-14 ZVS Curves Over AC Half Wave at Medium Load

As the trajectories illustrate, at the beginning of the grid sinusoid, the converter starts in mode III and then, due to increased voltage gain and load, transitions to mode II.

On light load, achieving Zero Voltage Switching (ZVS) for both primary and secondary side across zero crossing is easy, but achieving ZVS near to grid amplitude voltage is difficult. Conversely, at heavy load, the ZVS requirements for the distance between primary and secondary sides becomes narrower, making it hard to achieve ZVS across zero crossing. However, in this situation, achieving ZVS around grid amplitude voltage becomes easier.

There are two points where D1 and D2 are crossed – this is the mode transition point. There is no possibility of achieving ZVS for both primary lag and secondary sides because the turn-off current is very close to 0 at this point.

Equation 8 calculates how the controller uses a weighted sum from these two requirements to calculate the final value for D1.

Equation 8.

D 1 = α \times {D 1}_{P R I} + (1 - α) \times {D 1}_{S E C}, α \in (0, 1)

where

α is the weighting coefficient

The weighted coefficient can be used to balance behavior of the primary and secondary sides. If the coefficient comes close to 1, the final D1 going closer to primary ZVS requirement giving less room for ZVS realization for the primary side, in the same time giving more room for ZVS on the secondary side. Typically the C_OSS stored energy on the high-voltage switches is significantly higher and from the efficiency perspective, a balance with higher values for α gives slightly better results.