CD4007UB

ACTIVE

CMOS dual complementary pair plus inverter

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Product details

Parameters

Technology Family CD4000 VCC (Min) (V) 3 VCC (Max) (V) 18 Channels (#) 2 Inputs per channel 3 IOL (Max) (mA) 4 Input type Standard CMOS IOH (Max) (mA) -4 Output type Push-Pull Features Standard Speed (tpd > 50ns) Data rate (Max) (Mbps) 8 Rating Catalog Operating temperature range (C) -55 to 125 open-in-new Find other Combination gate

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other Combination gate

Features

  • Standardized symmetrical output characteristics
  • Medium Speed Operation — tPHL, tPLH = 30 ns (typ.) at 10 V
  • 100% tested for quiescent current at 20 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Applications:
    • Extremely high-input impedance amplifiers
    • Shapers
    • Inverters
    • Threshold detector
    • Linear amplifiers
    • Crystal oscillators

Data sheet acquired from Harris Semiconductor

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Description

CD4007UB types are comprised of three n-channel and three p-channel enhancement-type MOS transistors. The transistor elements are accessible through the package terminals to provide a convenient means for constructing the various typical circuits as shown in Fig. 2.

More complex functions are possible using multiple packages. Numbers shown in parentheses indicate terminals that are connected together to form the various configurations listed.

The CD4007UB types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 9
Type Title Date
* Datasheet CD4007UB TYPES datasheet (Rev. C) Aug. 21, 2003
Technical articles How to keep your motor running safely Jun. 04, 2020
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics Dec. 03, 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options
TSSOP (PW) 14 View options

Ordering & quality

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