CD54HCT30

ACTIVE

Military single 8-input, 4.5-V to 5.5-V NAND gate

Top

Product details

Parameters

Technology Family HCT Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Number of channels (#) 1 Inputs per channel 8 IOL (Max) (mA) 4 IOH (Max) (mA) -4 Input type TTL-Compatible CMOS Output type Push-Pull Features High speed (tpd 10- 50ns) Data rate (Max) (Mbps) 28 Rating Military open-in-new Find other NAND gate

Package | Pins | Size

CDIP (J) 14 130 mm² 19.94 x 6.73 open-in-new Find other NAND gate

Features

  • LSTTL input logic compatible
    • VIL(max) = 0.8 V, VIH(min) = 2 V
  • CMOS input logic compatible
    • II ≤ 1 µA at VOL, VOH
  • Buffered inputs
  • 4.5 V to 5.5 V operation
  • Wide operating temperature range: -55°C to +125°C
  • Supports fanout up to 10 LSTTL loads
  • Significant power reduction compared to LSTTL logic ICs

All trademarks are the property of their respective owners.

open-in-new Find other NAND gate

Description

This device contains one independent 8-input NAND gate. Each gate performs the Boolean function Y =  A ● B ● C ● D ● E ● F ● G ● H in positive logic.

open-in-new Find other NAND gate
Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 15
Type Title Date
* Data sheet CD54HCT30, CD74HCT30 High Speed CMOS Logic 8-Input NAND Gate datasheet Mar. 05, 2020
* SMD CD54HCT30 SMD 5962-89746 Jun. 21, 2016
Technical article How to keep your motor running safely Jun. 04, 2020
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

CAD/CAE symbols

Package Pins Download
CDIP (J) 14 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos