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CD74HC4040

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High Speed CMOS Logic 12-Stage Binary Counter

Data sheet
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High Speed CMOS Logic 12-Stage Binary Counter

CD74HC4040

ACTIVE
Data sheet Order now

Product details

Parameters

Function Counter Bits (#) 12 Technology Family HC VCC (Min) (V) 2 VCC (Max) (V) 6 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode open-in-new Find other Counter, arithmetic & parity function ICs

Package | Pins | Size

PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (D) 16 59 mm² 9.9 x 6 open-in-new Find other Counter, arithmetic & parity function ICs

Features

  • Fully Static Operation
  • Buffered Inputs
  • Common Reset
  • Negative Edge Pulsing
  • Fanout (Over Temperature Range)
    - Standard Outputs...10 LSTTL Loads
    - Bus Driver Outputs...15 LSTTL Loads
  • Wide Operating Temperature Range... -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    - 2V to 6V Operation
    - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    - 4.5V to 5.5V Operation
    - Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    - CMOS Input Compatibility, Il 1µA at VOL, VOH
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Description

The ’HC4040 and ’HCT4040 are 14-stage ripple-carry binary counters. All counter stages are master-slave flip-flops. The state of the stage advances one count on the negative clock transition of each input pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 15
Type Title Date
* Datasheet CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040 datasheet (Rev. D) Oct. 16, 2003
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

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Hardware development

EVALUATION BOARD Download
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
View details

Reference designs

REFERENCE DESIGNS Download
Multiparameter front end reference design for vital signs patient monitor
TIDA-01614 — This reference design is for a multiparameter front end of a patient monitor that measures vital sign parameters like ECG, heart rate, SpO2 and respiration.it uses biosensing front end integrated circuits like the AFE4403 and ADS1292R devices, to measure these parameters. It also uses three TMP117 (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
PDIP (N) 16 View options
SOIC (D) 16 View options

Ordering & quality

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  • MTBF/FIT estimates
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  • Ongoing reliability monitoring

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