The HC4060 and HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition of O). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times.
In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same as in the HC4060; only the MR input in the HCT4060 has TTL switching levels.
Data sheet acquired from Harris Semiconductor
|Part number||Order||Technology Family||VCC (Min) (V)||VCC (Max) (V)||Bits (#)||Voltage (Nom) (V)||F @ nom voltage (Max) (MHz)||ICC @ nom voltage (Max) (mA)||tpd @ nom Voltage (Max) (ns)||IOL (Max) (mA)||IOH (Max) (mA)||Function||Type||Rating||Operating temperature range (C)||Package Group|
|28||0.08||64||5.2||-5.2||Counter||Binary||Catalog||-55 to 125||
PDIP | 16
SOIC | 16
TSSOP | 16
|CD54HC4060||Samples not available||HC||2||6||14||
|28||0.08||64||5.2||-5.2||Counter||Binary||Military||-55 to 125||CDIP | 16|