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CDCEL913-Q1

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Automotive catalog programmable 1-PLL VCXO clock synthesizer with 1.8-V LVCMOS outputs

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Data sheet

CDCEL913-Q1

ACTIVE
Data sheet Order now

Product details

Function Clock generator, Spread-spectrum clock generator Number of outputs 3 Output frequency (max) (MHz) 230 Core supply voltage (V) 1.8 Output supply voltage (V) 1.8 Input type LVCMOS, XTAL Output type LVCMOS Operating temperature range (°C) -40 to 85 Features I2C, Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Automotive
Function Clock generator, Spread-spectrum clock generator Number of outputs 3 Output frequency (max) (MHz) 230 Core supply voltage (V) 1.8 Output supply voltage (V) 1.8 Input type LVCMOS, XTAL Output type LVCMOS Operating temperature range (°C) -40 to 85 Features I2C, Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Automotive
TSSOP (PW) 14 32 mm² 5 x 6.4
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grades
      • Grade 1 For CDCE913-Q1: –40°C to +125°C Ambient Operating Temperature
      • Grade 3 For CDCEL913-Q1: –40°C to +85°C Ambient Operating Temperature
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C6
  • In-System Programmability and EEPROM
    • Serial Programmable Volatile Register
    • Nonvolatile EEPROM to Store Customer Settings
  • Flexible Input Clocking Concept
    • External Crystal: 8 MHz to 32 MHz
    • On-Chip VCXO: Pull Range ±150 ppm
    • Single-Ended LVCMOS up to 160 MHz
  • Free Selectable Output Frequency up to 230  MHz
  • Low-Noise PLL Core
    • PLL Loop Filter Components Integrated
    • Low Period Jitter (Typical 50 ps)
  • Separate Output Supply Pins
    • CDCE913-Q1: 3.3 V and 2.5 V
    • CDCEL913-Q1: 1.8 V
  • Flexible Clock Driver
    • Three User-Definable Control Inputs [S0, S1, S2], for Example, SSC Selection, Frequency Switching, Output Enable, or Power Down
    • Generates Highly Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Bluetooth, WLAN, Ethernet, and GPS
    • Generates Common Clock Frequencies Used With TI-DaVinci, OMAP, DSPs
    • Programmable SSC Modulation
    • Enables 0-PPM Clock Generation
  • 1.8-V Device Power Supply
  • Packaged in TSSOP
  • Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock)

All trademarks are the property of their respective owners.

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grades
      • Grade 1 For CDCE913-Q1: –40°C to +125°C Ambient Operating Temperature
      • Grade 3 For CDCEL913-Q1: –40°C to +85°C Ambient Operating Temperature
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C6
  • In-System Programmability and EEPROM
    • Serial Programmable Volatile Register
    • Nonvolatile EEPROM to Store Customer Settings
  • Flexible Input Clocking Concept
    • External Crystal: 8 MHz to 32 MHz
    • On-Chip VCXO: Pull Range ±150 ppm
    • Single-Ended LVCMOS up to 160 MHz
  • Free Selectable Output Frequency up to 230  MHz
  • Low-Noise PLL Core
    • PLL Loop Filter Components Integrated
    • Low Period Jitter (Typical 50 ps)
  • Separate Output Supply Pins
    • CDCE913-Q1: 3.3 V and 2.5 V
    • CDCEL913-Q1: 1.8 V
  • Flexible Clock Driver
    • Three User-Definable Control Inputs [S0, S1, S2], for Example, SSC Selection, Frequency Switching, Output Enable, or Power Down
    • Generates Highly Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Bluetooth, WLAN, Ethernet, and GPS
    • Generates Common Clock Frequencies Used With TI-DaVinci, OMAP, DSPs
    • Programmable SSC Modulation
    • Enables 0-PPM Clock Generation
  • 1.8-V Device Power Supply
  • Packaged in TSSOP
  • Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock)

All trademarks are the property of their respective owners.

The CDCE913-Q1 and CDCEL913-Q1 devices are modular, phase-locked loop (PLL) based programmable clock synthesizers. These devices provide flexible and programmable options, such as output clocks, input signals, and control pins, so that the user can configure the CDCEx913-Q1 for their own specifications.

The CDCEx913-Q1 generates up to three output clocks from a single input frequency to enable both board space and cost savings. Additionally, with multiple outputs, the clock generator can replace multiple crystals with one clock generator. This makes the device well-suited for head unit and telematics applications in infotainment and camera systems in ADAS as these platforms are evolving into smaller and more cost effective systems.

Furthermore, each output can be programmed in-system for any clock frequency up to 230 MHz through the integrated, configurable PLL. The PLL also supports spread-spectrum clocking (SSC) with programmable down and center spread. This provides better electromagnetic interference (EMI) performance to enable customers to pass industry standards such as CISPR-25.

Customization of frequency programming and SSC are accessed using three, user-defined control pins. This eliminates the need to use an additional interface to control the clock. Specific power-up and power-down sequences can also be defined to the user’s needs.

For all available packages, see the orderable addendum at the end of the data sheet.

The CDCE913-Q1 and CDCEL913-Q1 devices are modular, phase-locked loop (PLL) based programmable clock synthesizers. These devices provide flexible and programmable options, such as output clocks, input signals, and control pins, so that the user can configure the CDCEx913-Q1 for their own specifications.

The CDCEx913-Q1 generates up to three output clocks from a single input frequency to enable both board space and cost savings. Additionally, with multiple outputs, the clock generator can replace multiple crystals with one clock generator. This makes the device well-suited for head unit and telematics applications in infotainment and camera systems in ADAS as these platforms are evolving into smaller and more cost effective systems.

Furthermore, each output can be programmed in-system for any clock frequency up to 230 MHz through the integrated, configurable PLL. The PLL also supports spread-spectrum clocking (SSC) with programmable down and center spread. This provides better electromagnetic interference (EMI) performance to enable customers to pass industry standards such as CISPR-25.

Customization of frequency programming and SSC are accessed using three, user-defined control pins. This eliminates the need to use an additional interface to control the clock. Specific power-up and power-down sequences can also be defined to the user’s needs.

For all available packages, see the orderable addendum at the end of the data sheet.
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Technical documentation

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Type Title Date
* Data sheet CDCEx913-Q1 Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs datasheet (Rev. C) PDF | HTML 09 Nov 2016
Technical article How to select an optimal clocking solution for your FPGA-based design 09 Dec 2015
Technical article Clocking sampled systems to minimize jitter 31 Jul 2014
Application note Crystal or Crystal Oscillator Replacement with Silicon Devices 18 Jun 2014
Technical article Timing is Everything: How to optimize clock distribution in PCIe applications 28 Mar 2014
Application note VCXO Application Guideline for CDCE(L)9xx Family (Rev. A) 23 Apr 2012
Application note General I2C / EEPROM usage for the CDCE(L)9xx family 26 Jan 2010
Application note Troubleshooting I2C Bus Protocol 19 Oct 2009
Application note Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 23 Sep 2009
Application note Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency 31 Mar 2008

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