Dual-Channel, 16-Bit, 2.8-GSPS, 1x-16x Interpolating Digital-to-Analog Converter (DAC)


Product details


Resolution (Bits) 16 DAC channels 2 Interface JESD204B Sample/update rate (MSPS) 2800 Features Ultra High Speed Rating Catalog Interpolation 16x, 1x, 2x, 4x, 8x Power consumption (Typ) (mW) 1135 SFDR (dB) 81 Architecture Current Source Operating temperature range (C) -40 to 85 Reference: type Int open-in-new Find other High-speed DACs (>10MSPS)

Package | Pins | Size

FCBGA (AAV) 144 100 mm² 10 x 10 open-in-new Find other High-speed DACs (>10MSPS)


  • Resolution: 16-Bit
  • Maximum Sample Rate: 2.8GSPS
  • Maximum Input Data Rate: 1.4GSPS
  • JESD204B Interface
    • 8 JESD204B Serial Input Lanes
    • 12.5 Gbps Maximum Bit Rate per Lane
    • Subclass 1 Multi-DAC synchronization
  • On-Chip Very Low Jitter PLL
  • Selectable 1x -16x Interpolation
  • Independent Complex Mixers with 48-bit NCO/
    or ±n×Fs/8
  • Wideband Digital Quadrature Modulator Correction
  • Sinx/x Correction Filters
  • Fractional Sample Group Delay Correction
  • Flexible Routing to Four Analog Outputs via Output
  • 3/4-Wire Serial Control Bus (SPI)
  • Integrated Temperature Sensor
  • JTAG Boundary Scan
  • Pin-compatible with Quad-channel DAC39J84
  • Power Dissipation: 1.1W at 2.8GSPS
  • Package: 10x10mm, 144-Ball Flip-Chip BGA
open-in-new Find other High-speed DACs (>10MSPS)


The DAC39J82 is a very low power, 16-bit, dual-channel, 2.8 GSPS digital to analog converter (DAC) with JESD204B interface. The maximum input data rate is 1.4 GSPS.

Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.

The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.

A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.

DAC39J82 provides four analog outputs, and the data from the internal two digital paths can be routed to any two out of these four DAC outputs via the output multiplexer.

open-in-new Find other High-speed DACs (>10MSPS)

Technical documentation

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No results found. Please clear your search and try again. View all 8
Type Title Date
* Datasheet DAC39J82 Dual-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface datasheet Jan. 26, 2015
Application notes DAC3xJ8x Device Initialization and SYSREF Configuration Sep. 27, 2017
Technical articles Digital signal processing in RF sampling DACs – part 2 Apr. 04, 2017
Technical articles Digital signal processing in RF sampling DACs - part 1 Feb. 13, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
User guides DAC3XJ8XEVM User's Guide (Rev. B) Apr. 28, 2016
Technical articles RF sampling: frequency planning yields a clean spectrum Nov. 18, 2015
Application notes System solution for avionics & defense Sep. 23, 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

 The DAC39J82EVM is an evaluation module (EVM) designed to evaluate the DAC39J82EVMhigh-speed, JESD204B interface DAC. The EVM includes an onboard clocking solution (LMK04828), transformer coupled outputs, full power solution, and easy-to-use software GUI and USB interface.

The DAC39J82EVM is designed (...)

  • Allows comprehensive testing of the DAC39J82 high-speed, JESD204B interface DAC
  • Transformer-coupled signal path enables direct performance testing of the DAC39J82 outputs
  • Simplified testing using the onboard LMK04828 JESD204B clocking solution for clock generation, jitter cleaning, or distribution
  • Easy (...)
SLAC644B.ZIP (219583 KB)

Design tools & simulation

SLAM197.ZIP (50 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

Reference designs

Synchronized Multi-Transmitter Reference Design: Method of Time-Aligning Multiple DACs
TIDA-00996 To further increase the range, data rate, and reliability of modern mobile communications systems, system designers continue to place more emphasis on multiple-antenna transmitter systems to achieve combinations of spatial diversity and spatial multiplexing. Such implementations can further (...)
document-generic Schematic document-generic User guide
High Bandwidth, High Frequency Transmitter Reference Design
TIDA-00335 This design illustrates the circuit modifications required to support high bandwidth and  high frequency applications using current source DACs like the  DAC38J84 with the TRF3704 modulator.  The TRF3704 is a 6 GHz modulator capable of supporting wide BB bandwidths.  The DAC38J84 (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

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FCBGA (AAV) 144 View options

Ordering & quality

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