DAC37J84

• Resolution: 16-Bit
• Maximum Sample Rate:
  • DAC37J84: 1.6 GSPS
  • DAC38J84: 2.5 GSPS
• Maximum Input Data Rate: 1.23GSPS
• JESD204B Interface
  • 8 JESD204B Serial Input Lanes
  • 12.5 Gbps Maximum Bit Rate per Lane
  • Subclass 1 Multi-DAC Synchronization
• On-Chip Very Low Jitter PLL
• Selectable 1x -16x Interpolation
• Independent Complex Mixers with 48-bit NCO/
  or ±n×Fs/8
• Wideband Digital Quadrature Modulator Correction
• Sinx/x Correction Filters
• Fractional Sample Group Delay Correction
• Multi-Band Mode: Digital Summation of Independent
  Complex Signals
• 3/4-Wire Serial Control Bus (SPI):1.5V – 1.8V
• Integrated Temperature Sensor
• JTAG Boundary Scan
• Terminal-Compatible with Dual-Channel DAC37J82/
  DAC38J82 Family
• Power Dissipation: 1.8W at 2.5GSPS
• Package: 10x10mm, 144-Ball Flip-Chip BGA

The terminal-compatible DAC37J84/DAC38J84 family is a low power, 16-bit, quad-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface.

Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.

The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.

A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.