Quad-Channel, 16-Bit, 1.6-GSPS, 1x-16x Interpolating Digital-to-Analog Converter (DAC)
Product details
Parameters
Package | Pins | Size
Features
- Resolution: 16-Bit
- Maximum Sample Rate:
- DAC37J84: 1.6 GSPS
- DAC38J84: 2.5 GSPS
- Maximum Input Data Rate: 1.23GSPS
- JESD204B Interface
- 8 JESD204B Serial Input Lanes
- 12.5 Gbps Maximum Bit Rate per Lane
- Subclass 1 Multi-DAC Synchronization
- On-Chip Very Low Jitter PLL
- Selectable 1x -16x Interpolation
- Independent Complex Mixers with 48-bit NCO/
or ±n×Fs/8 - Wideband Digital Quadrature Modulator Correction
- Sinx/x Correction Filters
- Fractional Sample Group Delay Correction
- Multi-Band Mode: Digital Summation of Independent
Complex Signals - 3/4-Wire Serial Control Bus (SPI):1.5V – 1.8V
- Integrated Temperature Sensor
- JTAG Boundary Scan
- Terminal-Compatible with Dual-Channel DAC37J82/
DAC38J82 Family - Power Dissipation: 1.8W at 2.5GSPS
- Package: 10x10mm, 144-Ball Flip-Chip BGA
Description
The terminal-compatible DAC37J84/DAC38J84 family is a low power, 16-bit, quad-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface.
Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.
The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.
A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The DAC3XJ8XEVM is an evaluation module (EVM) designed to evaluate the DAC3XJ8X family of high-speed, JESD204B interface DACs (DAC37J82, DAC37J84, DAC38J82, DAC38J84). The EVM includes an onboard clocking solution (LMK04828), transformer coupled outputs, full power solution, and easy-to-use software (...)
Features
- Allows comprehensive testing of the DAC3XJ8X family of high-speed, JESD204B interface DACs
- Transformer-coupled signal path enables direct performance testing of the DAC3XJ8X outputs
- Simplified testing using the onboard LMK04828 JESD204B clocking solution for clock generation, jitter cleaning, or (...)
Software development
Features
- Compatible with JEDEC JESD204a/b/c protocols
- Supports subclass 1 deterministic latency and multidevice synchronization
- Supported lane rates
- Up to 16.375 Gbps in 8b/10b mode
- Up to 20 Gbps in 64b/66b mode
- Supports all protocol related error detection and reporting features
- Integrated transport layer (...)
Features
- Compatible with TSW1400, TSW1405, TSW1406 and TSW14J10, TSW14J50, TSW14J56, and TSW14J57 pattern-generation and data-capture platforms
- Works with all TI high-speed DAC, ADC, and AFE products
- Provides time-domain and frequency-domain analysis
- Supports single-tone, multi-tone, and modulated (...)
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
Reference designs
Design files
-
download TIDA-00409 BOM.pdf (126KB) -
download TIDA-00409 Gerber.zip (2605KB)
Design files
-
download TIDA-00996 Assembly Drawing (DAC3XJ8X EVM).pdf (98KB) -
download TIDA-00996 PCB Layer Plots (DAC3XJ8X EVM).pdf (1779KB) -
download TIDA-00996 CAD Files (DAC3XJ8X EVM).zip (1954KB) -
download TIDA-00996 Design Package (DAC3XJ8X EVM).zip (5583KB) -
download TIDA-00996 Gerber (DAC3XJ8X EVM).zip (583KB) -
download TIDA-00996 BOM (DAC3XJ8X EVM).pdf (74KB)
Design files
-
download TIDA-00335 BOM.pdf (53KB) -
download TIDA-00335 Gerber.zip (855KB)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
FCBGA (AAV) | 144 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
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