The terminal-compatible DAC37J84/DAC38J84 family is a low power, 16-bit, quad-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface.
Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.
The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.
A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | Quad-Channel, 16-Bit, 1.6/2.5 GSPS, Digital-to-Analog Converters datasheet (Rev. B) | 24 Mar 2014 | |
| Application note | DAC3xJ8x Device Initialization and SYSREF Configuration | 27 Sep 2017 | ||
| EVM User's guide | DAC3XJ8XEVM User's Guide (Rev. B) | 28 Apr 2016 | ||
| EVM User's guide | TSW3XJ8XEVM User's Guide (Rev. B) | 09 Mar 2016 | ||
| Application note | System solution for avionics & defense | 23 Sep 2015 | ||
| White paper | Ready to make the jump to JESD204B? White Paper (Rev. B) | 19 Mar 2015 | ||
| Technical article | JESD204B: How to measure and verify your deterministic latency | 27 Feb 2015 | ||
| EVM User's guide | Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report (Rev. A) | 15 Sep 2014 | ||
| Design guide | Analog Interfacing Networks for DAC348x and Modulators (TIDA-00077) (Rev. A) | 14 Aug 2013 | ||
| Application note | High Speed, Digital-to-Analog Converters Basics (Rev. A) | 23 Oct 2012 |
For additional terms or required resources, click any title below to view the detail page where available.
The DAC3XJ8XEVM is an evaluation module (EVM) designed to evaluate the DAC3XJ8X family of high-speed, JESD204B interface DACs (DAC37J82, DAC37J84, DAC38J82, DAC38J84). The EVM includes an onboard clocking solution (LMK04828), transformer coupled outputs, full power solution, and easy-to-use (...)
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
| Package | Pins | Download |
|---|---|---|
| FCCSP (AAV) | 144 | View options |
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.
The design resource accessed as www.ti.com/lit/zip/slwc107 or www.ti.com/lit/xx/slwc107w/slwc107w.zip has been migrated to a new user experience at www.ti.com/tool/download/SLWC107. Please update any bookmarks accordingly.