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Product details

Parameters

Output options Fixed Output Iout (Max) (A) 0.15 Vin (Max) (V) 5.5 Vin (Min) (V) 2.5 Vout (Max) (V) 4.5 Vout (Min) (V) 1.5 Fixed output options (V) 1.5, 1.575, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2.5, 2.6, 2.65, 2.7, 2.75, 2.8, 2.85, 3.0, 3.3, 4.5 Noise (uVrms) 6.5 Iq (Typ) (mA) 0.025 Thermal resistance θJA (°C/W) 80 Load capacitance (Min) (µF) 0.47 Rating Catalog Regulated outputs (#) 1 Features Enable Accuracy (%) 3 PSRR @ 100 KHz (dB) 40 Dropout voltage (Vdo) (Typ) (mV) 80 Operating temperature range (C) -40 to 125 open-in-new Find other Linear regulators (LDO)

Package | Pins | Size

DSBGA (YPF) 4 0 mm² 1.117 x 1.092 DSBGA (YZR) 4 2 mm² 1.117 x 1.092 WSON (NGF) 6 6 mm² 2.2 x 2.5 open-in-new Find other Linear regulators (LDO)

Features

  • Input Voltage Range, 2.5 V to 5.5 V
  • Output Voltage Range, 1.5 V to 4.5 V
  • Stable with 0.47-μF Ceramic Input and Output Capacitors
  • No Noise Bypass Capacitor Required
  • Logic Controlled Enable
  • Thermal-Overload and Short-Circuit Protection
  • −40°C to 125°C Junction Temperature Range for Operation
  • Output Current, 150 mA
  • Low Output Voltage Noise, 6.5 μVRMS
  • PSRR, 75 dB at 1 kHz
  • Output Voltage Tolerance, ±2%
  • Virturally Zero IQ (Disabled), < 1 µA
  • Very Low IQ (Enabled), 25 μA
  • Start-up Time, 150 μs
  • Low Dropout, 80 mV Typ.
open-in-new Find other Linear regulators (LDO)

Description

The LP5900 is an LDO capable of supplying 150-mA output current. Designed to meet the requirements of RF and analog circuits, the LP5900 device provides low noise, high PSRR, low quiescent current, and low line transient response figures. Using new innovative design techniques the LP5900 offers class-leading device noise performance without a noise bypass capacitor.

The device is designed to work with 0.47-μF input and output ceramic capacitors (no bypass capacitor required).

The device is available in a DSBGA (YZR) package and a WSON package; the device is also available in an extremely thin DSBGA (YPF) package. For all voltage and package options available today, see the Package Option Addendum (POA) at the end of this data sheet. For any other fixed output voltages from 1.5 V to 4.5 V in 25-mV steps and all other package options, contact your local TI Sales office.

For all available packages, see the orderable addendum at the end of the data sheet.
open-in-new Find other Linear regulators (LDO)
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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 15
Type Title Date
* Datasheet LP5900 150-mA Ultra-Low-Noise LDO for RF and Analog Circuits - Requires No Bypass Capacitor datasheet (Rev. R) Jun. 01, 2016
Technical articles LDO basics: capacitor vs. capacitance Aug. 01, 2018
Technical articles LDO Basics: Preventing reverse current Jul. 25, 2018
Selection guide Power Management Guide 2018 (Rev. R) Jun. 25, 2018
Technical articles LDO basics: introduction to quiescent current Jun. 20, 2018
Selection guide Low Dropout Regulators Quick Reference Guide (Rev. P) Mar. 21, 2018
Technical articles LDO basics: noise – part 1 Jun. 14, 2017
User guide AN-1494 LP5900SD 6 Pin WSON Evaluation Board Information (Rev. B) Apr. 30, 2013
User guide AN-1396 LP5900 DSBGA Evaluation Board Information (Rev. C) Apr. 29, 2013
Application note AN-2145 Power Considerations for SDI Products (Rev. B) Apr. 26, 2013
Application note AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) Apr. 26, 2013
Application note AN-1950 Silently Powering Low Noise Applications (Rev. A) Apr. 22, 2013
User guide High-IF Sub-sampling Receiver Subsystem User Guide Jan. 27, 2012
User guide SP16130CH4RB Low IF Receiver Reference Design User Guide Jan. 27, 2012
White paper Using Power to Improve Signal-Path Performance Aug. 01, 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
399
Description

The LMK05028EVM is an evaluation module for the LMK05028 Network Clock Generator and Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping.
The LMK05028 integrates two Digital PLLs (DPLLs) with programmable bandwidth for input wander and jitter (...)

Features
  • Dual DPLLs with programmable bandwidths and Analog PLLs for frequency translation
  • 4 clock inputs supporting hitless switching and holdover
  • 8 differential or 16 LVCMOS output clocks or combination of both 
  • On-chip EEPROM for custom start-up clock clocks
  • Flexible oscillator options: onboard XOs, TCXO, or (...)
EVALUATION BOARD Download
399
Description
The LMK05318EVM is an evaluation module for the LMK05318 Network Synchronizer Clock device.
The EVM can be used as a flexible, synchronous clock source for rapid evaluation, compliance testing, and system prototyping.  SMA ports provide access to the LMK05318 clock inputs and outputs for (...)
Features
  • One Digital PLL (DPLL) with programmable bandwidths and Two Fractional Analog PLLs (APLLs) for Flexible Clock Generation
  • Two reference inputs to the DPLL supporting hitless switching & holdover
  • Eight output clocks with 50-fs RMS phase jitter (12 kHz to 20 MHz)
  • On-chip EEPROM for custom start-up clock (...)
EVALUATION BOARD Download
99
Description

The LMK61E0MEVM evaluation modules provides a complete platform to evaluate the jitter performance and configurability of the Texas Instruments LMK61E0M Ultra-Low Jitter Programmable Oscillator with integrated EEPROM and extended frequency margining capabilities.

The LMK61E0MEVM can be used as (...)

Features
  • Ultra low jitter dual output LVCMOS clock generation
  • Powered over USB or externally (SMA connector)
  • Onboard USB to I2C interface
  • Coarse and Fine Frequency margining
  • GUI platform for full access to registers and EEPROM
EVALUATION BOARD Download
99
Description

The LMK61E2EVM evaluation modules provides a complete platform to evaluate the 90-fs RMS jitter performance and configurability of the Texas Instruments LMK61E2 Ultra-Low Jitter Programmable Differential Oscillator with integrated EEPROM and frequency margining capabilities.

The LMK61E2EVM can be (...)

Features
  • Ultra low jitter differential clock generation
  • Powered over USB or externally (SMA connector)
  • Onboard USB to I2C interface
  • Coarse and Fine Frequency margining
  • GUI platform for full access to LMK03328 registers and EEPROM
EVALUATION BOARD Download
20
Description

The LP5900 is a linear regulator capable of supplying 150mA output current. Designed to meet the requirements of RF/Analog circuits, the LP5900 device provides low noise, high PSRR, low quiescent current, and low line transient response figures. Using new innovative design techniques the LP5900 (...)

Features
  • Stable with 0.47µF Ceramic Input and Output Capacitors
  • No Noise Bypass Capacitor Required
  • Logic Controlled Enable
  • Thermal-overload and short-circuit protection
  • -40°C to +125°C junction temperature range for operation

Key Specifications

  • Input Voltage Range: 2.5V to 5.5V
  • Output Voltage Range: 1.5V to 3.3V
  • Output (...)
EVALUATION BOARD Download
49
Description

The LP5900 is a linear regulator capable of supplying 150 mA output current. Designed to meet the requirements of RF/Analog circuits, the LP5900 device provides low noise, high PSRR, low quiescent current, and low line transient response figures. Using new innovative design techniques the LP5900 (...)

Features
  • Stable with 0.47 microF Ceramic Input and Output Capaciors
  • No Noise Bypass Capacitor Required
  • Logic Controlled Enable
  • Thermal-overload and short-circuit protection
  • -40°C to +125°C junction temperature range for operation

Key Specification:

  • Input voltage Range: 2.5V to 5.5V
  • Output voltage range: 1.5V to 3.3V
  • (...)
EVALUATION BOARD Download
49
Description

The LP5900 is a linear regulator capable of supplying 150 mA output current. Designed to meet the requirements of RF/Analog circuits, the LP5900 device provides low noise, high PSRR, low quiescent current, and low line transient response figures. Using new innovative design techniques the LP5900 (...)

Features
  • Stable with 0.47 microF Ceramic Input and Output Capaciors
  • No Noise Bypass Capacitor Required
  • Logic Controlled Enable
  • Thermal-overload and short-circuit protection
  • -40°C to +125°C junction temperature range for operation

Key Specification

  • Input voltage Range: 2.5V to 5.5V
  • Output voltage range: 1.5V to 3.3V
  • (...)
EVALUATION BOARD Download
49
Description

The LP5900 is a linear regulator capable of supplying 150 mA output current. Designed to meet the requirements of RF/Analog circuits, the LP5900 device provides low noise, high PSRR, low quiescent current, and low line transient response figures. Using new innovative design techniques the LP5900 (...)

Features
  • Stable with 0.47 microF Ceramic Input and Output Capaciors
  • No Noise Bypass Capacitor Required
  • Logic Controlled Enable
  • Thermal-overload and short-circuit protection
  • -40°C to +125°C junction temperature range for operation

Key Specification

  • Input voltage Range: 2.5V to 5.5V
  • Output voltage range: 1.5V to 3.3V
  • (...)

Design tools & simulation

SIMULATION MODEL Download
SNVM635.ZIP (41 KB) - PSpice Model
SIMULATION MODEL Download
SNVM636.ZIP (41 KB) - PSpice Model
SIMULATION MODEL Download
SNVM637.ZIP (42 KB) - PSpice Model
SIMULATION MODEL Download
SNVMAA4.ZIP (1 KB) - PSpice Model
SIMULATION MODEL Download
SNVMAA5.ZIP (1 KB) - PSpice Model
SIMULATION MODEL Download
SNVMAA6.ZIP (1 KB) - PSpice Model
CAD/CAE SYMBOL Download
SNAC011.ZIP (3372 KB)
CAD/CAE SYMBOL Download
SNAC012.ZIP (3259 KB)

Reference designs

REFERENCE DESIGNS Download
160-MHz Bandwidth Wireless Signal Tester Reference Design
TIDA-00988 — This reference design implements an IF subsystem for a standard wireless signal tester with an active balun-amplifier (LMH5401), LC bandpass filter, 16-bit ADC (ADC31JB68) and clock cleaner and generator PLL (LMK04828). Measurements using modulated signals demonstrate reception of the signal with (...)
document-generic Schematic
REFERENCE DESIGNS Download
Low Power RF PLL-Synthesizer Operating From a Single Cell Battery Reference Design
TIDA-00886 — The TIDA-00886 consists of the LMX2571,  high-performance, wideband PLLatinum™ low-power RF synthesizer, powered by a single cell battery using TPS63050 a DC-DC buck-boost converter.  The TIDA-00886 shows that the DC-DC buck-boost converter has a small to negligible effect on (...)
document-generic Schematic
REFERENCE DESIGNS Download
Linear Regulator Power Solution Reference Design for Reducing MSP430G2xx3 Power Dissipation
TIDA-00691 This linear regulator power solution provides power supply to MSP430 microcontroller. By implementing two linear regulator in parallell but work seperately, this power solution can reduce system power dissipation. Low quiescent current LP5900-3.3 and LP5900-1.8 are fit for this application.
document-generic Schematic
REFERENCE DESIGNS Download
Low Noise and Small Form Factor Power Management Reference Design for CC256X Bluetooth Controller
TIDA-00598 The TIDA-00598 features a low noise and size optimized power management solution which regulates 5V to 3.3V and 1.8V required to operate the CC256X Bluetooth controller.  These regulated voltage rails can also be used to power other components in the system as microcontroller, level shifters (...)
document-generic Schematic
REFERENCE DESIGNS Download
Cascaded LMH5401 and LMH6401 Reference Design
TIDA-00654 A wideband single-ended to differential conversion reference design in both DC- and AC- coupled applications is presented. The design evaluates the performance of the LMH5401 and LMH6401 cascade and offers insight into the design.
document-generic Schematic
REFERENCE DESIGNS Download
Power Solution for Terasic DE0-Nano (Cyclone IV) - Reference Design
PMP10580 The PMP10580 reference design provides all the power supply rails necessary to power Altera’s Cyclone® IV FPGA.  DE0-Nano was developed by Terasic and this board is available for purchase through Terasic’s website.
document-generic Schematic
Design files
REFERENCE DESIGNS Download
Altera Arria V GX FPGA Power Solution Reference Design
PMP9449 The PMP9449 reference design provides all the power supply rails necessary to power Altera's Arria® V GX family of FPGAs.  It utilizes a TPS38600 to monitor the input supply and provide power on sequencing.  This design features low cost, small footprint discrete ICs and is powered (...)
document-generic Schematic
REFERENCE DESIGNS Download
JESD204B Link Latency Design Using a High Speed ADC
TIDA-00153 JESD204B links are the latest trend in data-converter digital interfaces. These links take advantage of high-speed serial-digital technology to offer many compelling benefits including improved channel densities. This reference design addresses one of the challenges of adopting the new interface (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
DSBGA (YPF) 4 View options
DSBGA (YZR) 4 View options
WSON (NGF) 6 View options

Ordering & quality

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