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Product details

Parameters

Operating temperature range (C) -40 to 85 open-in-new Find other Other interfaces

Package | Pins | Size

NFBGA (NZA) 49 49 mm² 7 x 7 open-in-new Find other Other interfaces

Features

  • Compatible with IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan Architecture
  • Supported by Texas Instruments' SCAN Ease (SCAN Embedded Application Software Enabler) Software Rev 2.0
  • Uses Generic, Asynchronous Processor Interface; Compatible with a Wide Range of Processors and Processor Clock (PCLK) Frequencies
  • 16-Bit Data Interface (IP Scalable to 32-bit)
  • 2k x 32 Bit Dual-Port Memory
  • Load-on-the-Fly (LotF) and Preloaded Vector Operating Modes Supported
  • On-Board Sequencer Allows Multi-Vector Operations such as those Required to Load Data Into an FPGA
  • On-Board Compares Support Test Data In (TDI) Validation Against Preloaded Expected Data
  • 32-Bit Linear Feedback Shift Register (LFSR) at the Test Data In (TDI) Port for Signature Compression
  • State, Shift, and BIST Macros Allow Predetermined Test Mode Select (TMS) Sequences to be Utilized
  • Operates at 3.3 V Supply Voltages with 5 V Tolerant I/O
  • Outputs Support Power-Down TRI-STATE Mode.

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Description

The SCANSTA101 is designed to function as a test master for an IEEE 1149.1 boundary scan test system. It is suitable for use in embedded IEEE 1149.1 applications and as a component in a stand-alone boundary scan tester.

The SCANSTA101 is an enhanced version of, and a replacement for, the SCANPSC100. The SCANSTA101 supports the IEEE 1149.1 Test Access Port (TAP) standard and the IEEE 1532 standard for in-system configuration of programmable devices.

The SCANSTA101 improves test vector throughput and reduces software overhead in the system processor. The SCANSTA101 presents a simple, register-based interface to the system processor. Texas Instruments provides C-language source code which can be included in the embedded system software. The combination of the SCANSTA101 and its support software comprises a simple API for boundary scan operations.

The interface from the SCANSTA101 to the system processor is implemented by reading and writing registers, some of which map to locations in the SCANSTA101 memory. Hardware handshaking and interrupt lines are provided as part of the processor interface.

The SCANSTA101 is available as a stand-alone device packaged in a 49-pin NFBGA package. It is also available as an IP macro for synthesis in programmable logic devices.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 3
Type Title Date
* Datasheet SCANSTA101 Low Voltage IEEE 1149.1 System Test Access (STA) Master datasheet (Rev. J) Apr. 12, 2013
Application notes SCANSTA101 Quick Reference Guide Jan. 07, 2010
Application notes JTAG Advanced Capabilities and System Design Mar. 19, 2009

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Software development

APPLICATION SOFTWARE & FRAMEWORKS Download
EVF Workbench - Converts JTAG SVF to TI's EVF2 SCAN Format
EVF-WORKBENCH-CONVERTER-SW — Graphical User Interface tool for conversion of SVF files to Texas Instrument’s EVF2 embedded file format. Zip file includes readme file, license file, and setup program (1.6MB)

Design tools & simulation

SIMULATION MODELS Download
SNLM006.ZIP (4 KB) - IBIS Model
SIMULATION TOOLS Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SIMULATION TOOLS Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
NFBGA (NZA) 49 View options

Ordering & quality

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