Product details


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NFBGA (NZD) 100 100 mm² 10 x 10 TQFP (NEZ) 100 256 mm² 16 x 16 open-in-new Find other Other interfaces


  • True IEEE 1149.1 Hierarchical and Multidrop Addressable Capability
  • The 8 Address Inputs Support up to 249 Unique Slot Addresses, an Interrogation Address, Broadcast Address, and 4 Multi-Cast Group Addresses (Address 000000 is Reserved)
  • 7 IEEE 1149.1-Compatible Configurable Local Scan Ports
  • Bi-directional Backplane and LSP0 Ports are Interchangeable Slave Ports
  • Capable of Ignoring TRST of the Backplane Port when it Becomes the Slave.
  • Stitcher Mode Bypasses Level 1 and 2 Protocols
  • Mode Register0 Allows Local TAPs to be Bypassed, Selected for Insertion into the Scan Chain Individually, or Serially in Groups of Two or Three
  • Transparent Mode can be Enabled with a Single Instruction to Conveniently Buffer the Backplane IEEE 1149.1 Pins to Those on a Single Local Scan Port
  • General Purpose Local Port Pass Through Bits are Useful for Delivering Write Pulses for Flash Programming or Monitoring Device Status.
  • Known Power-Up State
  • TRST on all Local Scan Ports
  • 32-bit TCK Counter
  • 16-bit LFSR Signature Compactor
  • Local TAPs can Become TRI-STATE via the OE Input to Allow an Alternate Test Master to Take Control of the Local TAPs (LSP0-3 have a TRI-STATE Notification Output)
  • 3.0-3.6V VCC Supply Operation
  • Supports Live Insertion/Withdrawal

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The SCANSTA112 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANSTA112 supports up to 7 local IEEE1149.1 scan chains which can be accessed individually or combined serially.

Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested.

The STA112 has a unique feature in that the backplane port and the LSP0 port are bidirectional. They can be configured to alternatively act as the master or slave port so an alternate test master can take control of the entire scan chain network from the LSP0 port while the backplane port becomes a slave.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 9
Type Title Date
* Datasheet SCANSTA112 7-Port Multidrop IEEE 1149.1 (JTAG) Multiplexer datasheet (Rev. I) Apr. 12, 2013
Application notes AN-1259 SCANSTA112 Designer's Reference (Rev. H) Apr. 26, 2013
Application notes AN-1312 SCANSTA111/SCANSTA112 Scan Bridge Timing (Rev. B) Apr. 26, 2013
Application notes Simplified Program of Xilinx Devices Using a SCANSTA111/112 JTAG Scan Chain Mux (Rev. C) Apr. 26, 2013
Application notes Simplified Programming of Altera FPGAs Using CSANSTA111/112 JTAG Scan Chain Mux (Rev. D) Apr. 26, 2013
More literature SCANSTA112 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer Evaluation Kit Docume Feb. 21, 2012
Application notes SCANSTA112 Quick Reference Guide Jan. 07, 2010
Application notes JTAG Advanced Capabilities and System Design Mar. 19, 2009
Application notes Partition IEEE 1149.1 SCAN Chains for Manageability! Mar. 06, 2003

Design & development

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Software development

EVF Workbench - Converts JTAG SVF to TI's EVF2 SCAN Format
EVF-WORKBENCH-CONVERTER-SW — Graphical User Interface tool for conversion of SVF files to Texas Instrument’s EVF2 embedded file format. Zip file includes readme file, license file, and setup program (1.6MB)

Design tools & simulation

SNLM151.ZIP (5 KB) - IBIS Model
SNLM195.ZIP (3 KB) - BSDL Model
SNLM196.ZIP (3 KB) - BSDL Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide
SNLC004.PDF (88 KB)

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