Top

Product details

Parameters

Technology Family AC VCC (Min) (V) 2 VCC (Max) (V) 6 Channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 24 IOH (Max) (mA) -24 Input type Standard CMOS Output type Push-Pull Features Over-Voltage Tolerant Inputs, Very High Speed (tpd 5-10ns) Data rate (Max) (Mbps) 100 Rating Space Operating temperature range (C) -55 to 125 open-in-new Find other NAND gate

Package | Pins | Size

CDIP (J) 14 CFP (W) 14 open-in-new Find other NAND gate

Features

  • 5962R87549:
    • Radiation Hardness Assurance (RHA) up to TID
      TID 100 krad (Si)
    • SEL/SEU Immune to 86 MeV
  • 5962-87549:
    • Total Ionizing Dose 50 krad (Si)
  • 2-V to 6-V VCC Operation
  • Inputs Accept Voltages to 6 V
  • Max tpd of 7 ns at 5 V
open-in-new Find other NAND gate

Description

The SN54AC00 device contains four independent 2-input NAND gates. Each gate performs the Boolean function of Y = A • B or Y = A + B in positive logic.

open-in-new Find other NAND gate
Download

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 19
Type Title Date
* Datasheet SN54AC00-SP Radiation Hardened Quad 2 Input NAND Gate datasheet (Rev. B) Feb. 09, 2015
* SMD SN54AC00-SP SMD 5962-87549 Jul. 08, 2016
* Radiation & Reliability reports 54AC00-SP Radiation Assured Devices Apr. 21, 2016
Technical articles How to keep your motor running safely Jun. 04, 2020
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing Jun. 17, 2019
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
White papers 54AC00-SP 50-krad TID Report Mar. 26, 2015
More literature HiRel Unitrode Power Management Brochure Jul. 07, 2009
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Design tools & simulation

SIMULATION MODELS Download
SCHM007.ZIP (22 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
(KGD) 0 View options
CDIP (J) 14 View options
CFP (W) 14 View options

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos

Related videos