Product details

Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type TTL-Compatible CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 90 Rating Catalog Operating temperature range (°C) -40 to 85
Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type TTL-Compatible CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 90 Rating Catalog Operating temperature range (°C) -40 to 85
PDIP (N) 14 181.42 mm² 19.3 x 9.4 SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4
  • 4.5V to 5.5V VCC operation
  • Inputs accept voltages to 5.5V
  • Max tpd of 10ns at 5V
  • Inputs are TTL-voltage compatible
  • 4.5V to 5.5V VCC operation
  • Inputs accept voltages to 5.5V
  • Max tpd of 10ns at 5V
  • Inputs are TTL-voltage compatible

The ’ACT32 devices are quadruple 2-input positive-OR gates. The devices perform the Boolean function Y = A + B or Y = A • B in positive logic.

The ’ACT32 devices are quadruple 2-input positive-OR gates. The devices perform the Boolean function Y = A + B or Y = A • B in positive logic.

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Technical documentation

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Type Title Date
* Data sheet SN74ACT32 Quadruple 2-Input Positive-or Gates datasheet (Rev. D) PDF | HTML 24 Jul 2024
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74ACT32 Behavioral SPICE Model

SCAM121.ZIP (7 KB) - PSpice Model
Simulation model

SN74ACT32 IBIS Model

SCAM031.ZIP (15 KB) - IBIS Model
Package Pins CAD symbols, footprints & 3D models
PDIP (N) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian

Ordering & quality

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  • Ongoing reliability monitoring
Information included:
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  • Assembly location

Support & training

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