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SN74ALS112A

ACTIVE
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Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset

Data sheet
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Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset

SN74ALS112A

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Data sheet Order now

Product details

Parameters

Channels (#) 2 Technology Family ALS VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Input type TTL Output type TTL Clock Frequency (MHz) 34 ICC (Max) (uA) 4000 IOL (Max) (mA) 8 IOH (Max) (mA) -0.4 Features Negative edge triggered, High speed (tpd 10-50ns), Preset, Clear open-in-new Find other J-K flip-flop

Package | Pins | Size

PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (D) 16 59 mm² 9.9 x 6 SOP (NS) 16 80 mm² 10.2 x 7.8 open-in-new Find other J-K flip-flop

Features

  • Fully Buffered to Offer Maximum Isolation From External Disturbance
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

 

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Description

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs, regardless of the levels of the other inputs. When and are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

The SN54ALS112A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS112A is characterized for operation from 0°C to 70°C.

 

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Technical documentation

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Type Title Date
* Datasheet Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset datasheet (Rev. A) Dec. 01, 1994
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note Advanced Schottky (ALS and AS) Logic Families Aug. 01, 1995

Design & development

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Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
View details

CAD/CAE symbols

Package Pins Download
PDIP (N) 16 View options
SO (NS) 16 View options
SOIC (D) 16 View options

Ordering & quality

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