SN74ALS112A Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset | TI.com

SN74ALS112A
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Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset

 

Description

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs, regardless of the levels of the other inputs. When and are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

The SN54ALS112A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS112A is characterized for operation from 0°C to 70°C.

 

Features

  • Fully Buffered to Offer Maximum Isolation From External Disturbance
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

 

Parametrics

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Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Bits (#) Voltage (Nom) (V) F @ nom voltage (Max) (MHz) ICC @ nom voltage (Max) (mA) tpd @ nom Voltage (Max) (ns) IOL (Max) (mA) IOH (Max) (mA) Rating
SN74ALS112A Order now ALS     4.5     5.5     2     5     75     4.5     18     8     -0.4     Catalog    
SN54ALS112A Samples not available ALS     4.5     5.5     2     5     75     4.5     18     -0.4     8     Military