Product details


Technology Family ALS VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Bits (#) 4 Voltage (Nom) (V) 5 F @ nom voltage (Max) (MHz) 75 ICC @ nom voltage (Max) (mA) 36 tpd @ nom Voltage (Max) (ns) 29 IOL (Max) (mA) 24 IOH (Max) (mA) -2.6 Function Counter Product type Binary Rating Catalog Operating temperature range (C) 0 to 70 open-in-new Find other Counter, arithmetic & parity function ICs

Package | Pins | Size

PDIP (N) 20 229 mm² 24.33 x 9.4 open-in-new Find other Counter, arithmetic & parity function ICs


  • Carry Output for n-Bit Cascading
  • Buffer-Type Outputs Drive Bus Lines Directly
  • Choice of Asynchronous or Synchronous Clearing and Loading
  • Internal Look-Ahead Circuitry for Fast Cascading
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
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These binary counters are programmable and offer synchronous and asynchronous clearing as well as synchronous and asynchronous loading. All synchronous functions are executed on the positive-going edge of the clock.

The clear function is initiated by applying a low level to either asynchronous clear (ACLR\) or synchronous clear (SCLR\). ACLR\ (direct clear) overrides all other functions of the device, while SCLR\ overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by applying a low level to asynchronous load (ALOAD\) or by the combination of a low level at synchronous load (SLOAD\) and a positive-going clock transition. The counting function is enabled only when enable P (ENP), enable T (ENT), ACLR\, ALOAD\, SCLR\, and SLOAD\ are all high.

A high level at the output-enable () input forces the Q outputs into the high-impedance state, and a low level enables those outputs. Counting is independent of OE\. ENT is fed forward to enable the ripple-carry output (RCO) to produce a high-level pulse while the count is maximum (15). The clocked carry output (CCO) produces a high-level pulse for a duration equal to that of the low level of the clock when RCO is high and the counter is enabled (ENP and ENT are high); otherwise, CCO is low. CCO does not have the glitches commonly associated with a ripple-carry output. Cascading is normally accomplished by connecting RCO or CCO of the first counter to ENT of the next counter. However, for very high-speed counting, RCO should be used for cascading because CCO does not become active until the clock returns to the low level.

The SN54ALS561A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS561A is characterized for operation from 0°C to 70°C.



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Technical documentation

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Type Title Date
* Datasheet Synchronous 4-Bit Counters With 3-State Outputs datasheet (Rev. A) Jan. 01, 1995
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Advanced Schottky (ALS and AS) Logic Families Aug. 01, 1995

Design & development

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Hardware development

document-generic User guide
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

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PDIP (N) 20 View options

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