SN74AUP1G80

1 mm² .8 x 1.2

2 mm² .928 x 1.428

5 mm² 2.9 x 1.6

4 mm² 2 x 2.1

1 mm² 1.5 x 1

1 mm² .8 x .8

1 mm² 1 x 1

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
  (A114-B, Class II)
- 1000-V Charged-Device Model (C101)
Available in the Texas Instruments NanoStar™ Package
Low Static-Power Consumption
(I_CC = 0.9 µA Maximum)
Low Dynamic-Power Consumption
(C_pd = 4.3 pF Typical at 3.3 V)
Low Input Capacitance (C_i = 1.5 pF Typical)
Low Noise – Overshoot and Undershoot <10% of V_CC
I_off Supports Partial-Power-Down Mode Operation
Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input
(V_hys = 250 mV Typical at 3.3 V)
Wide Operating V_CC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
t_pd = 4.4 ns Maximum at 3.3 V
Suitable for Point-to-Point Applications

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
  (A114-B, Class II)
- 1000-V Charged-Device Model (C101)
Available in the Texas Instruments NanoStar™ Package
Low Static-Power Consumption
(I_CC = 0.9 µA Maximum)
Low Dynamic-Power Consumption
(C_pd = 4.3 pF Typical at 3.3 V)
Low Input Capacitance (C_i = 1.5 pF Typical)
Low Noise – Overshoot and Undershoot <10% of V_CC
I_off Supports Partial-Power-Down Mode Operation
Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input
(V_hys = 250 mV Typical at 3.3 V)
Wide Operating V_CC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
t_pd = 4.4 ns Maximum at 3.3 V
Suitable for Point-to-Point Applications

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The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family assures a low static- and dynamic-power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in increased battery life (see AUP – The Lowest-Power Family). This product also maintains excellent signal integrity (see Excellent Signal Integrity).

This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

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Technical documentation

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	Type	Title	Date
*	Data sheet	SN74AUP1G80 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop datasheet (Rev. F)	20 Jul 2017
	Selection guide	Little Logic Guide 2018 (Rev. G)	06 Jul 2018
	Application note	Designing and Manufacturing with TI's X2SON Packages	23 Aug 2017
	Selection guide	Logic Guide (Rev. AB)	12 Jun 2017
	Application note	How to Select Little Logic (Rev. A)	26 Jul 2016
	Technical article	A race against the clock: how to determine the power-up states of clocked devices	06 Mar 2015
	Application note	Power-Up Behavior of Clocked Devices (Rev. A)	06 Feb 2015
	Application note	Understanding Schmitt Triggers	21 Sep 2011
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 Jul 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic EVM supporting 5 through 8 pin DCK, DCT, DCU, DRL, and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.

User guide

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Limit: 5

Simulation model

SN74AUP1G80 IBIS Model (Rev. B)

SCEM444B.ZIP (64 KB) - IBIS Model

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