SN74AUP1G80 Low-Power Single Postitive-Edge-Triggered D-Type Flip-Flop | TI.com

SN74AUP1G80
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Low-Power Single Postitive-Edge-Triggered D-Type Flip-Flop

Low-Power Single Postitive-Edge-Triggered D-Type Flip-Flop - SN74AUP1G80
Datasheet
SN74AUP1G80 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop datasheet (Rev. F)
 

Recommended alternative parts

  • SN74AUC1G80  -  Single D-Type Flip-Flop, Faster Speed - Tpd: 2.4ns

Description

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family assures a low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see AUP – The Lowest-Power Family). This product also maintains excellent signal integrity (see Excellent Signal Integrity).

This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

Features

  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4.3 pF Typical at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot <10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input
    (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.4 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications

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Parametrics

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Part number Order Technology Family Input type Output type VCC (Min) (V) VCC (Max) (V) Channels (#) Clock Frequency (Max) (MHz) ICC (uA) IOL (Max) (mA) IOH (Max) (mA) Features Rating Package Group
SN74AUP1G80 Order now AUP     Standard CMOS     Push-Pull     0.8     3.6     1     260     0.9     4     -4     Balanced outputs
Very high speed (tpd 5-10ns)
Over-voltage tolerant inputs
Partial power down (Ioff)    		 Catalog     DSBGA | 5
DSBGA | 6
SC70 | 5
SON | 6
SON | 6
SOT-23 | 5
X2SON | 5    
SN74AUC1G79 Samples not available AUC     Standard CMOS     Push-Pull     0.8     2.7     1     275     10     9     -9     Balanced outputs
Ultra high speed (tpd <5ns)
Over-voltage tolerant inputs
Partial power down (Ioff)    		 Catalog     SC70 | 5
SOT-23 | 5    
SN74AUP1G74 Order now AUP     Standard CMOS     Push-Pull     0.8     3.6     1     160     0.9     4     -4     Balanced outputs
Very high speed (tpd 5-10ns)
Over-voltage tolerant inputs
Partial power down (Ioff)    		 Catalog     DSBGA | 8
DSBGA | 8
UQFN | 8
VSSOP | 8
X2SON | 8    
SN74AUP1G79 Order now AUP     Standard CMOS     Push-Pull     0.8     3.6     1     260     0.9     4     -4     Balanced outputs
Very high speed (tpd 5-10ns)
Over-voltage tolerant inputs
Partial power down (Ioff)    		 Catalog     DSBGA | 5
DSBGA | 6
SC70 | 5
SON | 6
SON | 6
SOT-23 | 5
SOT-5X3 | 5
X2SON | 5    
SN74AUP2G79 Order now AUP     Standard CMOS     Push-Pull     0.8     3.6     2     260     0.9     4     -4     Balanced outputs
Very high speed (tpd 5-10ns)
Over-voltage tolerant inputs
Partial power down (Ioff)    		 Catalog     DSBGA | 8
UQFN | 8
VSSOP | 8
X2SON | 8    
SN74LVC1G79 Order now LVC     Standard CMOS     Push-Pull     1.65     5.5     1     150     10     32     -32