Low-Power Single Postitive-Edge-Triggered D-Type Flip-Flop
Product details
Parameters
Package | Pins | Size
Features
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II) - 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model
- Available in the Texas Instruments NanoStar™ Package
- Low Static-Power Consumption
(ICC = 0.9 µA Maximum) - Low Dynamic-Power Consumption
(Cpd = 4.3 pF Typical at 3.3 V) - Low Input Capacitance (Ci = 1.5 pF Typical)
- Low Noise – Overshoot and Undershoot <10% of VCC
- Ioff Supports Partial-Power-Down Mode Operation
- Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input
(Vhys = 250 mV Typical at 3.3 V) - Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- tpd = 4.4 ns Maximum at 3.3 V
- Suitable for Point-to-Point Applications
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Description
The AUP family is TIs premier solution to the industrys low-power needs in battery-powered portable applications. This family assures a low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see AUP – The Lowest-Power Family). This product also maintains excellent signal integrity (see Excellent Signal Integrity).
This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | SN74AUP1G80 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop datasheet (Rev. F) | Jul. 20, 2017 |
Selection guide | Little Logic Guide 2018 (Rev. G) | Jul. 06, 2018 | |
Application note | Designing and Manufacturing with TI's X2SON Packages | Aug. 23, 2017 | |
Selection guide | Logic Guide (Rev. AB) | Jun. 12, 2017 | |
Application note | How to Select Little Logic (Rev. A) | Jul. 26, 2016 | |
Technical articles | A race against the clock: how to determine the power-up states of clocked devices | Mar. 06, 2015 | |
Application note | Power-Up Behavior of Clocked Devices (Rev. A) | Feb. 06, 2015 | |
Application note | Understanding Schmitt Triggers | Sep. 21, 2011 | |
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | Jul. 08, 2004 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic devices
Design tools & simulation
Reference designs
Design files
-
download TIDA-01054 Assembly Drawing.pdf (858KB) -
download TIDA-01054 PCB.pdf (3668KB) -
download TIDA-01054 Gerber.zip (1236KB) -
download TIDA-01054 BOM (Rev. A).pdf (79KB) -
download TIDA-01054 Altium (Rev. A).zip (57322KB)
Design files
-
download TIDA-01055 BOM.pdf (231KB) -
download TIDA-01055 Assembly Drawing.pdf (872KB) -
download TIDA-01055 PCB.pdf (3715KB) -
download TIDA-01055 Altium.zip (17037KB) -
download TIDA-01055 Gerber.zip (1227KB)
Design files
-
download TIDA-01057 BOM.pdf (123KB) -
download TIDA-01057 Assembly Drawing.pdf (983KB) -
download TIDA-01057 PCB.pdf (4279KB) -
download TIDA-01057 Altium.zip (30897KB) -
download TIDA-01057 Gerber.zip (2100KB)
Design files
-
download TIDA-01056 BOM.pdf (124KB) -
download TIDA-01056 Assembly Drawing.pdf (810KB) -
download TIDA-01056 PCB.pdf (3442KB) -
download TIDA-01056 CAD Files.zip (2609KB) -
download TIDA-01056 Gerber.zip (1603KB)
Design files
-
download TIDA-01051 BOM.pdf (107KB) -
download TIDA-01051 Assembly Drawing.pdf (2002KB) -
download TIDA-01051 PCB.pdf (8638KB) -
download TIDA-01051 CAD Files.zip (15688KB) -
download TIDA-01051 Gerber.zip (1735KB)
Design files
-
download TIDA-01050 BOM.pdf (247KB) -
download TIDA-01050 Assembly Drawing.pdf (3862KB) -
download TIDA-01050 PCB.pdf (7143KB) -
download TIDA-01050 CAD Files.zip (2442KB) -
download TIDA-01050 Gerber.zip (1180KB)
Design files
-
download TIDA-01052 BOM.pdf (247KB) -
download TIDA-01052 Assembly Drawing.pdf (3862KB) -
download TIDA-01052 PCB.pdf (7170KB) -
download TIDA-01052 CAD Files.zip (11142KB) -
download TIDA-01052 Gerber.zip (1180KB)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
DSBGA (YFP) | 6 | View options |
DSBGA (YZP) | 5 | View options |
SC70 (DCK) | 5 | View options |
SON (DRY) | 6 | View options |
SON (DSF) | 6 | View options |
SOT-23 (DBV) | 5 | View options |
X2SON (DPW) | 5 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
TI E2E™ forums with technical support from TI engineers
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