Product details

Technology Family LS Number of channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 8 Input type Bipolar IOH (Max) (mA) 0 Output type Open-Collector Features High speed (tpd 10- 50ns) Data rate (Max) (Mbps) 35 Rating Catalog Operating temperature range (C) 0 to 70
Technology Family LS Number of channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 8 Input type Bipolar IOH (Max) (mA) 0 Output type Open-Collector Features High speed (tpd 10- 50ns) Data rate (Max) (Mbps) 35 Rating Catalog Operating temperature range (C) 0 to 70
PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6
  • Can Be Used as a 4-Bit Digital Comparator
  • Input Clamping Diodes Simplify System Design
  • Fully Compatible with Most TTL Circuits

 

  • Can Be Used as a 4-Bit Digital Comparator
  • Input Clamping Diodes Simplify System Design
  • Fully Compatible with Most TTL Circuits

 

The 'LS266 is comprised of four independent 2-input exclusive-NOR gates with open-collector outputs. The open-collector outputs permit tying outputs together for multiple-bit comparisons.

 

The 'LS266 is comprised of four independent 2-input exclusive-NOR gates with open-collector outputs. The open-collector outputs permit tying outputs together for multiple-bit comparisons.

 

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Technical documentation

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Type Title Date
* Data sheet Quadruple 2-Input Exclusive-NOR Gates With Open-Collector Outputs datasheet 01 Mar 1983
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Designing with the SN54/74LS123 (Rev. A) 01 Mar 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, P, N, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
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Limit: 5
Simulation model

SN74LS266 Behavioral SPICE Model

SDLM039.ZIP (7 KB) - PSpice Model
Package Pins Download
PDIP (N) 14 View options
SOIC (D) 14 View options

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