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SN74LVC1G11

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Single 3-input, 1.65-V to 5.5-V AND gate

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Data sheet
Single 3-input, 1.65-V to 5.5-V AND gate

SN74LVC1G11

ACTIVE
Data sheet Order now

Product details

Technology Family LVC Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 5.5 Number of channels (#) 1 Inputs per channel 3 IOL (Max) (mA) 32 IOH (Max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Partial power down (Ioff), Over-voltage tolerant inputs, Ultra high speed (tpd <5ns) Data rate (Max) (Mbps) 100 Rating Catalog Operating temperature range (C) -40 to 125, -40 to 85
Technology Family LVC Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 5.5 Number of channels (#) 1 Inputs per channel 3 IOL (Max) (mA) 32 IOH (Max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Partial power down (Ioff), Over-voltage tolerant inputs, Ultra high speed (tpd <5ns) Data rate (Max) (Mbps) 100 Rating Catalog Operating temperature range (C) -40 to 125, -40 to 85
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DSBGA (YZP) 6 2 mm² .928 x 1.428 SOT-23 (DBV) 6 5 mm² 2.9 x 1.6 SOT-SC70 (DCK) 6 4 mm² 2 x 2.1 USON (DRY) 6 1 mm² 1.5 x 1 X2SON (DSF) 6 1 mm² 1 x 1
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  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Maximum tpd of 4.1 ns at 3.3 V
  • Low Power Consumption, 10-µA Maximum ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Maximum tpd of 4.1 ns at 3.3 V
  • Low Power Consumption, 10-µA Maximum ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Partial-Power-Down Mode Operation
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The SN74LVC1G11 performs the Boolean function Y = A • B • C or Y = A\ + B\ + C\ in positive logic.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LVC1G11 performs the Boolean function Y = A • B • C or Y = A\ + B\ + C\ in positive logic.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technical documentation

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Type Title Date
* Data sheet SN74LVC1G11 Single 3-Input Positive-AND Gate datasheet (Rev. H) 10 Nov 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note LVC Characterization Information 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

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Simulation model

SN74LVC1G11 IBIS Model (Rev. A)

SCEM369A.ZIP (44 KB) - IBIS Model
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Simulation model

SN74LVC1G11 Behavioral SPICE Model

SCEM640.ZIP (8 KB) - PSpice Model
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Package Pins Download
DSBGA (YZP) 6 View options
SC70 (DCK) 6 View options
SON (DRY) 6 View options
SON (DSF) 6 View options
SOT-23 (DBV) 6 View options

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