SN74LVC74A

ACTIVE

Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset

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Product details

Parameters

Channels (#) 2 Technology Family LVC VCC (Min) (V) 1.65 VCC (Max) (V) 3.6 Input type Standard CMOS Output type Push-Pull Clock Frequency (Max) (MHz) 100 IOL (Max) (mA) 24 IOH (Max) (mA) -24 ICC (Max) (uA) 10 Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs open-in-new Find other D-type flip-flop

Package | Pins | Size

SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 VQFN (RGY) 14 12 mm² 3.5 x 3.5 open-in-new Find other D-type flip-flop

Features

  • Operate From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Maximum tpd of 5.2 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)
open-in-new Find other D-type flip-flop

Description

The SNx4LVC74A devices integrate two positive-edge triggered D-type flip-flops in one convenient device.

The SN54LVC74A is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC74A is designed for 1.65-V to 3.6-V VCC operation.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

The data I/Os and control inputs are overvoltage tolerant. This feature allows the use of these devices for down-translation in a mixed-voltage environment.

open-in-new Find other D-type flip-flop
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Technical documentation

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Type Title Date
* Datasheet SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset datasheet (Rev. U) Jan. 04, 2017
Selection guides Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes How to Select Little Logic (Rev. A) Jul. 26, 2016
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
Application notes Use of the CMOS Unbuffered Inverter in Oscillator Circuits Nov. 06, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
User guides LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) Dec. 18, 2002
Application notes Texas Instruments Little Logic Application Report Nov. 01, 2002
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application notes 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application notes Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS Mar. 27, 2002
More literature Military Low Voltage Solutions Apr. 04, 2001
Application notes Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes LVC Characterization Information Dec. 01, 1996
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
User guides Low-Voltage Logic (LVC) Designer's Guide Sep. 01, 1996
Application notes Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
EVALUATION BOARDS Download
document-generic User guide
20
Description
Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic and translation devices with included dual supply support
  • Board has 9 sections that can be broken apart for a smaller form factor

Design tools & simulation

SIMULATION MODELS Download
SCAM062A.ZIP (26 KB) - PSpice Model
SIMULATION MODELS Download
SCEM059A.ZIP (36 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options
VQFN (RGY) 14 View options

Ordering & quality

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