The SNx4LVC74A devices integrate two positive-edge triggered D-type flip-flops in one
The SN54LVC74A is designed for 2.7-V to 3.6-V VCC operation, and
the SN74LVC74A is designed for 1.65-V to 3.6-V VCC operation.
A low level at the preset (PRE) or clear
(CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high),
data at the data (D) input meeting the setup time requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse. Following the hold-time interval, data at the
D input can be changed without affecting the levels at the outputs.
The data I/Os and control inputs are overvoltage tolerant. This feature allows the use of
these devices for down-translation in a mixed-voltage environment.