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TPS25925

ACTIVE
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4.5-V to 5.5-V, 30mΩ, 2-5A eFuse

Data sheet
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4.5-V to 5.5-V, 30mΩ, 2-5A eFuse

TPS25925

ACTIVE
Data sheet Order now

Product details

Parameters

FET Internal Ron (Typ) (mOhm) 30 Vin (Min) (V) 4.5 Vin (Max) (V) 5.5 Vabsmax_cont (V) 20 Current limit (Min) (A) 2 Current limit (Max) (A) 5 Overcurrent response Current Limiting Current limit type Adjustable Fault response Auto Retry, Latch Off UL recognition UL2367, UL60950 open-in-new Find other eFuses & hot swap controllers

Package | Pins | Size

VSON (DRC) 10 9 mm² 3 x 3 open-in-new Find other eFuses & hot swap controllers

Features

  • 12-V eFuse – TPS25926x
  • 5-V eFuse – TPS25925x
  • Integrated 30-mΩ Pass MOSFET
  • Fixed Over-Voltage Clamp:
    • 6.1-V Clamp - TPS25925x
    • 15-V Clamp - TPS25926x
  • 2-A to 5-A Adjustable ILIMIT (±15% Accuracy)
  • Programmable VOUT Slew Rate, UVLO
  • Built-in Thermal Shutdown
  • UL 2367 Recognized – File No. E339631*
    • *RILIM ≤ 130 kΩ (5 A maximum)
  • Safe During Single Point Failure Test (UL60950)
  • Small Foot Print – 10L (3 mm × 3 mm) VSON
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Description

The TPS25925x/6x family of eFuses is a highly integrated circuit protection and power management solution in a tiny package. The devices use few external components and provide multiple protection modes. They are a robust defense against overloads, shorts circuits, voltage surges, excessive inrush current. Current limit level can be set with a single external resistor and current limit set has a typical accuracy of ±15%. Over voltage events are limited by internal clamping circuits to a safe fixed maximum, with no external components required. TPS25926x devices provide over voltage protection (OVP) for 12-V systems and TPS25925x devices for 5-V systems. In cases with particular voltage ramp requirements, a dV/dT pin is provided that can be programmed with a single capacitor to ensure proper output ramp rates.

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TPS2595 ACTIVE 2.7-V to 18-V, 34mΩ, 0.5-4A eFuse with over voltage protection in small WSON package This product has improved performance and a lower price.

Technical documentation

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Type Title Date
* Datasheet TPS25925x, TPS25926x Simple 5-V/12-V eFuse Protection Switches datasheet (Rev. B) Jun. 01, 2016
More literature TPS2592x UL Certificate of Compliance IEC 60950-1 Apr. 10, 2020
More literature UL Certificate of Compliance UL 2367 Apr. 10, 2020
Application note eFuse: Safety Certification and why it Matters Mar. 18, 2020
E-book 11 Ways to Protect Your Power Path white paper Jul. 03, 2019
Application note Basics of eFuses (Rev. A) Apr. 05, 2018
Application note Power Multiplexing Using Load Switches and eFuses (Rev. A) Jun. 20, 2017
User guide TPS259250-61EVM: Evaluation Module for TPS259250/61 Aug. 24, 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
75
Description

TPS259250-61EVM is functional demonstration of TPS25925/6 family of eFuses protection switches, TPS25925/6 efuse are a highly integrated circuit protection switches and power management solution in a very small package. The devices use few external components and provide multiple protection modes (...)

Features
  • 5V/12 operating voltage eFuse protection switch
  • Up to 5.1A Adjustable ILIMIT setting option using Jumpers
  • On board fault and power good LED’s
  • Linear output ramp (gate dV/dt control) option
  • On board test point access for all critical device pins
View details

Design tools & simulation

SIMULATION MODEL Download
SLVMB83B.ZIP (44 KB) - PSpice Model
SIMULATION MODEL Download
SLVMB84B.ZIP (44 KB) - PSpice Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
View details
CALCULATION TOOL Download
SLUC570.ZIP (109 KB)

Reference designs

REFERENCE DESIGNS Download
Multichannel RF transceiver clocking reference design for RADARs and wireless 5G testers
TIDA-010131 — Analog front end for high-speed end equipments like phased-array radars, wireless communication testers, and electronic warfare require synchronized, multipletransceiver signal chains. Each transceiver signal chain includes high-speed, analog-to-digital converters (ADCs), digital-to-analog (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers
TIDA-01023 — High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports high channel count JESD204B synchronized clocks using one master and multiple (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers
TIDA-01021 — High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers
TIDA-01024 — High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports scaling up JESD204B synchronized clocks in daisy chain configuration. This (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Precision Power Limiting Solution
TIDA-00331 — This solution limits the power delivered to a maximum of 15W to ensure IEC60730 compliance in Human-Machine-Interaction (HMI) ports, making it very easy for the end equipment to meet the safety regulations.
This design uses TI’s TPS25921AD to monitor the voltage and current flowing through the (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
VSON (DRC) 10 View options

Ordering & quality

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  • Qualification summary
  • Ongoing reliability monitoring

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