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Highspeed-ADCs (≥ 10 MSPS)

ADC12DJ5200-SEP

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Radiation-tolerant, 30krad, 12 bit, dual 5.2GSPS or single 10.4GSPS ADC

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Datenblatt

ADC12DJ5200-SEP

AKTIV
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Produktdetails

Sample rate (max) (Msps) 5200, 10400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 7900 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.825 Power consumption (typ) (mW) 4000 Architecture Folding Interpolating SNR (dB) 55.6 ENOB (Bits) 8.8 SFDR (dB) 65 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 30 Radiation, SEL (MeV·cm2/mg) 43
Sample rate (max) (Msps) 5200, 10400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 7900 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.825 Power consumption (typ) (mW) 4000 Architecture Folding Interpolating SNR (dB) 55.6 ENOB (Bits) 8.8 SFDR (dB) 65 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 30 Radiation, SEL (MeV·cm2/mg) 43
FCCSP (ALR) 144 100 mm² (10 mm × 10 mm)
  • Radiation Tolerance:
    • Total Ionizing Dose (TID): 30krad (Si)
    • Single Event Latchup (SEL): 43 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Space-enhanced plastic (space EP):
    • Meets ASTM E595 out-gassing specification
    • Vendor item drawing (VID) V62/22611
    • Temperature range: –55°C to 125°C
    • One fabrication, assembly, and test site
    • Wafer lot traceability
    • Extended product life cycle
    • Extended product change notification
  • ADC core:
    • 12-bit resolution
    • Up to 10.4GSPS in single-channel mode
    • Up to 5.2GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (–20dBFS, VFS = 1VPP-DIFF):
      • Dual-channel mode: –151.8dBFS/Hz
      • Single-channel mode: –154.4dBFS/Hz
    • ENOB (dual channel, FIN = 2.4GHz): 8.6 Bits
  • Buffered analog inputs with VCMI of 0V:
    • Analog input bandwidth (–3dB): 8GHz
    • Usable input frequency range: > 10GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19-fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Time stamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16Gbps
    • Support for 64b/66b and 8b/10b encoding
    • 8b/10b modes are JESD204B compatible
  • Optional digital down-converters (DDC):
    • Complex decimation: 4x (IBW = 0.2*FS = 2.08GHz in DES mode, 1.04GHz per channel in dual channel mode), 8x, 16x and 32x
    • Four independent 32-Bit NCOs per DDC
  • Peak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)
  • Programmable FIR filter for equalization
  • Power consumption: 4W
  • Power supplies: 1.1V, 1.9V
  • Radiation Tolerance:
    • Total Ionizing Dose (TID): 30krad (Si)
    • Single Event Latchup (SEL): 43 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Space-enhanced plastic (space EP):
    • Meets ASTM E595 out-gassing specification
    • Vendor item drawing (VID) V62/22611
    • Temperature range: –55°C to 125°C
    • One fabrication, assembly, and test site
    • Wafer lot traceability
    • Extended product life cycle
    • Extended product change notification
  • ADC core:
    • 12-bit resolution
    • Up to 10.4GSPS in single-channel mode
    • Up to 5.2GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (–20dBFS, VFS = 1VPP-DIFF):
      • Dual-channel mode: –151.8dBFS/Hz
      • Single-channel mode: –154.4dBFS/Hz
    • ENOB (dual channel, FIN = 2.4GHz): 8.6 Bits
  • Buffered analog inputs with VCMI of 0V:
    • Analog input bandwidth (–3dB): 8GHz
    • Usable input frequency range: > 10GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19-fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Time stamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16Gbps
    • Support for 64b/66b and 8b/10b encoding
    • 8b/10b modes are JESD204B compatible
  • Optional digital down-converters (DDC):
    • Complex decimation: 4x (IBW = 0.2*FS = 2.08GHz in DES mode, 1.04GHz per channel in dual channel mode), 8x, 16x and 32x
    • Four independent 32-Bit NCOs per DDC
  • Peak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)
  • Programmable FIR filter for equalization
  • Power consumption: 4W
  • Power supplies: 1.1V, 1.9V

The ADC12DJ5200-SEP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10GHz. ADC12DJ5200-SEP can be configured as a dual-channel, 5.2GSPS ADC or single-channel, 10.4GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ5200-SEP uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multichannel applications. Optional digital down converters (DDCs) are available to provide digital conversion to base-band and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.

The ADC12DJ5200-SEP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10GHz. ADC12DJ5200-SEP can be configured as a dual-channel, 5.2GSPS ADC or single-channel, 10.4GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ5200-SEP uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multichannel applications. Optional digital down converters (DDCs) are available to provide digital conversion to base-band and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.
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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt ADC12DJ5200-SEP 10.4GSPS Single-Channel or 5.2GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. A) PDF | HTML 08.04.2025
* Strahlungs- und Zuverlässigkeitsbericht ADC12DJ5200-SEP Production Flow and Reliability Report (Rev. A) PDF | HTML 12.03.2025

Design und Entwicklung

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Evaluierungsplatine

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Simulationsmodell

ADC12DJ5200RF IBIS and IBIS-AMI Model (Rev. A)

SLVMD65A.ZIP (49879 KB) - IBIS-AMI-Modell
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Berechnungstool

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