The CDCE949-Q1 is a modular PLL-based low-cost high-performance programmable clock synthesizer, multiplier, and divider. The device generates up to 9 output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230MHz, using up to four independent configurable PLLs.
The CDCE949-Q1 has separate output supply pins, VDDOUT, of 2.5V to 3.3V.
The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0pF to 20pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.
The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, BlueTooth™, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27MHz.
All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This technique is common for reducing electro-magnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.
The device supports non-volatile EEPROM programming for easy customization to the application. The CDCE949-Q1 is preset to a factory-default configuration (see the Default Device Configuration section). The device can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA/SCL bus, a 2-wire serial interface.
Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for the output-disable function.
The CDCE949-Q1 operates in a 1.8V environment. The device operates within a temperature range of –40°C to 125°C.
| Top-Dokumentation | Typ | Titel | Format-Optionen | Datum |
|---|---|---|---|---|
| * | Data sheet | CDCE949-Q1: Programmable 4-PLL VCXO Clock Synthesizer With 1.8V, 2.5V, and 3.3V LVCMOS Outputs datasheet (Rev. A) | PDF | HTML | 30 Mai 2025 |
| Application note | Crystal or Crystal Oscillator Replacement with Silicon Devices | 18 Jun 2014 | ||
| Application note | VCXO Application Guideline for CDCE(L)9xx Family (Rev. A) | 23 Apr 2012 | ||
| Application note | General I2C / EEPROM usage for the CDCE(L)9xx family | 26 Jan 2010 | ||
| Application note | Troubleshooting I2C Bus Protocol | 19 Okt 2009 | ||
| Application note | Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 | 23 Sep 2009 | ||
| Application note | Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency | 31 Mär 2008 |
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| Gehäuse | Pins | CAD-Symbole, Footprints und 3D-Modelle |
|---|---|---|
| TSSOP (PW) | 24 | Ultra Librarian |
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