Produktdetails

Protocols Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART Configuration 2:1 SPDT Number of channels 4 Bandwidth (MHz) 100 Supply voltage (max) (V) 3.6 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 5 CON (typ) (pF) 4 OFF-state leakage current (max) (µA) 10 Ron (max) (mΩ) 8000 VIH (min) (V) 1.7 VIL (max) (V) 0.8 Rating Catalog
Protocols Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART Configuration 2:1 SPDT Number of channels 4 Bandwidth (MHz) 100 Supply voltage (max) (V) 3.6 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 5 CON (typ) (pF) 4 OFF-state leakage current (max) (µA) 10 Ron (max) (mΩ) 8000 VIH (min) (V) 1.7 VIL (max) (V) 0.8 Rating Catalog
TSSOP (PW) 16 32 mm² 5 x 6.4 TVSOP (DGV) 16 23.04 mm² 3.6 x 6.4
  • Output voltage translation tracks VCC
  • Supports mixed-mode signal operation on all data I/O ports
    • 5V input down to 3.3V output level shift with 3.3V VCC
    • 5V/3.3V input down to 2.5V output level shift with 2.5V VCC
  • 5V-tolerant I/Os with device powered up or powered down
  • Bidirectional data flow with near-zero propagation delay
  • Low ON-state resistance (ron) characteristics (ron = 5Ω typ)
  • Low input/output capacitance minimizes loading (Cio(OFF) = 5pF typ)
  • Data and control inputs provide undershoot clamp diodes
  • Low power consumption (ICC = 20µA max)
  • VCC operating range from 2.3V to 3.6V
  • Data I/Os support 0V to 5V signaling levels (0.8V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5V)
  • Control inputs can be driven by TTL or 5V/3.3V CMOS outputs
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 250mA per JESD 17
  • ESD performance tested per JESD 22
    • 2000V human-body model (A114-B, Class II)
    • 1000V charged-device model (C101)
  • Output voltage translation tracks VCC
  • Supports mixed-mode signal operation on all data I/O ports
    • 5V input down to 3.3V output level shift with 3.3V VCC
    • 5V/3.3V input down to 2.5V output level shift with 2.5V VCC
  • 5V-tolerant I/Os with device powered up or powered down
  • Bidirectional data flow with near-zero propagation delay
  • Low ON-state resistance (ron) characteristics (ron = 5Ω typ)
  • Low input/output capacitance minimizes loading (Cio(OFF) = 5pF typ)
  • Data and control inputs provide undershoot clamp diodes
  • Low power consumption (ICC = 20µA max)
  • VCC operating range from 2.3V to 3.6V
  • Data I/Os support 0V to 5V signaling levels (0.8V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5V)
  • Control inputs can be driven by TTL or 5V/3.3V CMOS outputs
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 250mA per JESD 17
  • ESD performance tested per JESD 22
    • 2000V human-body model (A114-B, Class II)
    • 1000V charged-device model (C101)

The SN74CB3T3257 is a high-speed TTL-compatible FET multiplexer/demultiplexer with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T3257 supports systems using 5V TTL, 3.3V LVTTL, and 2.5V CMOS switching standards, as well as user-defined switching levels.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature verifies that damaging current does not backflow through the device when the device is powered down. The device has isolation during power off.

The SN74CB3T3257 is a high-speed TTL-compatible FET multiplexer/demultiplexer with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T3257 supports systems using 5V TTL, 3.3V LVTTL, and 2.5V CMOS switching standards, as well as user-defined switching levels.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature verifies that damaging current does not backflow through the device when the device is powered down. The device has isolation during power off.

Herunterladen Video mit Transkript ansehen Video

Technische Dokumentation

star =Von TI ausgewählte Top-Empfehlungen für dieses Produkt
Keine Ergebnisse gefunden. Bitte geben Sie einen anderen Begriff ein und versuchen Sie es erneut.
Alle anzeigen 15
Typ Titel Datum
* Data sheet SN74CB3T3257 4-Bit 1-of-2 FET Multiplexer/Demultiplexer 2.5V/3.3V Low-Voltage Bus Switch With 5V-Tolerant Level Shifter datasheet (Rev. A) PDF | HTML 27 Mai 2025
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 02 Jun 2022
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 01 Dez 2021
Application note CBT-C, CB3T, and CB3Q Signal-Switch Families (Rev. C) PDF | HTML 19 Nov 2021
Application brief Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) PDF | HTML 06 Jan 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Digital Bus Switch Selection Guide (Rev. A) 10 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Bus FET Switch Solutions for Live Insertion Applications 07 Feb 2003
Selection guide Logic Guide (Rev. AC) PDF | HTML 01 Jun 1994

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Schnittstellenadapter

LEADED-ADAPTER1 — Oberflächenmontierbarer DIP-Header-Adapter zur schnellen Prüfung der 5-, 8-, 10-, 16- und 24-poligen

Die EVM-LEADED1-Platine ermöglicht schnelles Testen und Testbrettaufbauten von gängigen bleihaltigen Gehäusen von TI.  Die Platine verfügt über Anschlussflächen, um die oberflächenmontierten Gehäuse D, DBQ, DCT,DCU, DDF, DGS, DGV und PW von TI in 100-mil-DIP-Stiftleisten umzuwandeln.     

Benutzerhandbuch: PDF
Simulationsmodell

HSPICE Model for SN74CB3T3257

SCDM117.ZIP (102 KB) - HSpice Model
Simulationsmodell

SN74CB3T3257 IBIS Model

SCDM059.ZIP (25 KB) - IBIS Model
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
TSSOP (PW) 16 Ultra Librarian
TVSOP (DGV) 16 Ultra Librarian

Bestellen & Qualität

Beinhaltete Information:
  • RoHS
  • REACH
  • Bausteinkennzeichnung
  • Blei-Finish/Ball-Material
  • MSL-Rating / Spitzenrückfluss
  • MTBF-/FIT-Schätzungen
  • Materialinhalt
  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
Beinhaltete Information:
  • Werksstandort
  • Montagestandort

Empfohlene Produkte können Parameter, Evaluierungsmodule oder Referenzdesigns zu diesem TI-Produkt beinhalten.

Support und Schulungen

TI E2E™-Foren mit technischem Support von TI-Ingenieuren

Inhalte werden ohne Gewähr von TI und der Community bereitgestellt. Sie stellen keine Spezifikationen von TI dar. Siehe Nutzungsbedingungen.

Bei Fragen zu den Themen Qualität, Gehäuse oder Bestellung von TI-Produkten siehe TI-Support. ​​​​​​​​​​​​​​

Videos