Gehäuseinformationen
| Gehäuse | Pins SOIC (D) | 16 |
| Betriebstemperaturbereich (°C) -40 to 125 |
| Gehäusemenge | Träger 2.500 | LARGE T&R |
Merkmale von UCC21222-Q1
- Universal: dual low-side, dual high-side or half-bridge driver
- AEC Q100 qualified with:
- Device temperature grade 1
- Device HBM ESD classification level H2
- Device CDM ESD classification level C4B
- Junction temperature range –40°C to 150°C
- 4A peak source, 6A peak sink output
- Common-mode transient immunity (CMTI) greater than 125V/ns
- Up to 25V VDD output drive supply
- 8V VDD UVLO
- Switching parameters:
- 33ns typical propagation delay
- 5ns maximum pulse-width distortion
- 10µs maximum VDD power-up delay
- UVLO protection for all power supplies
- Fast disable for power sequencing
Beschreibung von UCC21222-Q1
The UCC21222-Q1 device is an isolated dual channel gate driver with programmable dead time and a wide temperature range. This device exhibits consistent performance and robustness under extreme temperature conditions. It is designed with 4A peak-source and 6A peak-sink current to drive power MOSFET, IGBT, and GaN transistors.
The UCC21222-Q1 device can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. A 5ns delay matching performance allows two outputs to be paralleled, doubling the drive strength for heavy load conditions without risk of internal shoot-through.
The input side is isolated from the two output drivers by a 3.0kVRMS isolation barrier, with a minimum of 125V/ns common-mode transient immunity (CMTI).
Resistor programmable dead time gives the capability to adjust dead time for system constraints to improve efficiency and prevent output overlap. Other protection features include a disable feature to shut down both outputs simultaneously when DIS is set high, an integrated deglitch filter that rejects input transients shorter than 5ns, and negative voltage handling for up to –2V spikes for 200ns on input and output pins. All supplies have UVLO protection.