CDC7005

ACTIVO

Sincronizador de reloj de bajo sesgo de alto rendimiento y bajo ruido de fase que sincroniza el relo

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document-pdfAcrobat 3.3-V High Performance Clock Synthesizer & Jitter Cleaner datasheet (Rev. L) (Inglés)

CDC7005

ACTIVO

Hoja de datos

Haga su pedido ahora

Detalles del producto

Number of outputs

5

Output type

LVPECL

Output frequency (max) (MHz)

800

Core supply voltage (V)

3.3

Output supply voltage (V)

3.3

Input type

LVCMOS, LVPECL

Operating temperature range (°C)

-40 to 85

Features

Op-amp for active loop filter, Programmable delay

Rating

Catalog

Number of outputs

5

Output type

LVPECL

Output frequency (max) (MHz)

800

Core supply voltage (V)

3.3

Output supply voltage (V)

3.3

Input type

LVCMOS, LVPECL

Operating temperature range (°C)

-40 to 85

Features

Op-amp for active loop filter, Programmable delay

Rating

Catalog

BGA (ZVA)

64

64 mm² 8 x 8

VQFN (RGZ)

48

49 mm² 7 x 7

High Performance 1:5 PLL Clock Synchronizer
Two Clock Inputs: VCXO_IN Clock Is Synchronized to REF_IN Clock
Synchronizes Frequencies up to 800 MHz (VCXO_IN)
Supports Five Differential LVPECL Outputs
Each Output Frequency Is Selectable by x1, /2, /4, /8, /16
All Outputs Are Synchronized
Integrated Low-Noise OPA for External Low-Pass Filter
Efficient Jitter Screening From Low PLL Loop Bandwidth
Low-Phase Noise Characteristic
Programmable Delay for Phase Adjustments
Predivider Loop BW Adjustment
SPI Controllable Division Setting
Power-Up Control Forces LVPECL Outputs to 3-State at VCC <1.5 V
3.3-V Power Supply
Packaged In 64-Pin BGA (0,8 mm Pitch - ZVA) or 48-Pin QFN (RGZ)
Industrial Temperature Range –40°C to 85°C

High Performance 1:5 PLL Clock Synchronizer
Two Clock Inputs: VCXO_IN Clock Is Synchronized to REF_IN Clock
Synchronizes Frequencies up to 800 MHz (VCXO_IN)
Supports Five Differential LVPECL Outputs
Each Output Frequency Is Selectable by x1, /2, /4, /8, /16
All Outputs Are Synchronized
Integrated Low-Noise OPA for External Low-Pass Filter
Efficient Jitter Screening From Low PLL Loop Bandwidth
Low-Phase Noise Characteristic
Programmable Delay for Phase Adjustments
Predivider Loop BW Adjustment
SPI Controllable Division Setting
Power-Up Control Forces LVPECL Outputs to 3-State at VCC <1.5 V
3.3-V Power Supply
Packaged In 64-Pin BGA (0,8 mm Pitch - ZVA) or 48-Pin QFN (RGZ)
Industrial Temperature Range –40°C to 85°C

The CDC7005 is a high-performance, low-phase noise, and low-skew clock synchronizer and jitter cleaner that synchronizes the voltage controlled crystal oscillator (VCXO) frequency to the reference clock. The programmable predividers M and N give a high flexibility to the frequency ratio of the reference clock to VCXO: VCXO_IN/REF_IN = (NxP)/M. The VCXO_IN clock operates up to 800 MHz. Through the selection of external VCXO and loop filter components, the PLL loop bandwidth and damping factor can be adjusted to meet different system requirements. Each of the five differential LVPECL outputs is programmable by the serial peripheral interface (SPI). The SPI allows individual control of frequency and enable/disable state of each output. The device operates in 3.3-V environment. The built-in latches ensure that all outputs are synchronized.

The CDC7005 is characterized for operation from –40°C to 85°C.

The CDC7005 is a high-performance, low-phase noise, and low-skew clock synchronizer and jitter cleaner that synchronizes the voltage controlled crystal oscillator (VCXO) frequency to the reference clock. The programmable predividers M and N give a high flexibility to the frequency ratio of the reference clock to VCXO: VCXO_IN/REF_IN = (NxP)/M. The VCXO_IN clock operates up to 800 MHz. Through the selection of external VCXO and loop filter components, the PLL loop bandwidth and damping factor can be adjusted to meet different system requirements. Each of the five differential LVPECL outputs is programmable by the serial peripheral interface (SPI). The SPI allows individual control of frequency and enable/disable state of each output. The device operates in 3.3-V environment. The built-in latches ensure that all outputs are synchronized.

The CDC7005 is characterized for operation from –40°C to 85°C.

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Documentación técnica

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	Tipo	Título	Fecha
*	Data sheet	3.3-V High Performance Clock Synthesizer & Jitter Cleaner datasheet (Rev. L)	04 jun 2009
	Application brief	Using The CDC7005 as a 1:5 PECL Buffer w/Programmable Divider Ratio (Rev. B)	15 dic 2009
	Application note	Basics of the CDC7005 Hold Function	13 abr 2006
	User guide	CDC7005 (QFN Package) Evaluation Module Manual (Rev. B)	28 mar 2006
	Application note	Phase Noise (Jitter) Performance of CDC7005 With Different VCXOs (Rev. A)	19 jul 2005
	Application note	Open Loop Phase-Noise Performance of CDC7005 at Various Frequencies	17 dic 2004
	User guide	TSW2000 Receive Clock JItter Cleaning EVM	28 jun 2004
	Application note	Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC Dev	25 jun 2004
	Product overview	ADS5500 + CDC7005 Product Bulletin	23 jun 2004
	Product overview	TSW2000: TLK1201A & CDC7005	23 jun 2004
	Application note	General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner (Rev. A)	16 dic 2003
	Application note	General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner	21 mar 2003

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Soporte de software

SCAC037 — CDC7005 SPI Software with Labview 8.0 Runtime Engine

Productos y hardware compatibles

Productos

Generadores de señal de reloj

CDC7005 — Sincronizador de reloj de bajo sesgo de alto rendimiento y bajo ruido de fase que sincroniza el relo

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Modelo de simulación

CDC7005 IBIS Model

SCAC033.ZIP (34 KB) - IBIS Model

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Lista de materiales (BOM)

TSW1000 EVM Bill of Materials

SLWR028.ZIP (166 KB)

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Herramienta de cálculo

CDC-CDCM7005-CALC — Calculadora de ancho de banda de bucle PLL CDC7005 y CDCM7005

This tool helps to determine the right divider values (M, N & P) and to choose the filter type and components. This calculator will help to find out the appropriate loop bandwidth, phase margin, jitter peaking, etc. just varying the loop parameters like PFD frequency, filter components, Charge pump (...)

View Options

Archivo Gerber

CDC7005 EVM QFN Gerber Files

SCAC066.ZIP (537 KB)

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Archivo Gerber

TSW1000 EVM Gerber Files

SLWC050.ZIP (532 KB)

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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® para TI es un entorno de diseño y simulación que ayuda a evaluar la funcionalidad de los circuitos analógicos. Esta completa suite de diseño y simulación utiliza un motor de análisis analógico de Cadence®. Disponible sin ningún costo, PSpice para TI incluye una de las bibliotecas de modelos (...)

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Encapsulado	Pines	Símbolos CAD, huellas y modelos 3D
BGA (ZVA)	64	Ultra Librarian
VQFN (RGZ)	48	Ultra Librarian

Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

CDC7005

Sincronizador de reloj de bajo sesgo de alto rendimiento y bajo ruido de fase que sincroniza el relo

CDC7005

Detalles del producto

Documentación técnica

Diseño y desarrollo

SCAC037 — CDC7005 SPI Software with Labview 8.0 Runtime Engine

Productos y hardware compatibles

Productos

Generadores de señal de reloj

CDC7005 IBIS Model

TSW1000 EVM Bill of Materials

CDC-CDCM7005-CALC — Calculadora de ancho de banda de bucle PLL CDC7005 y CDCM7005

CDC7005 EVM QFN Gerber Files

TSW1000 EVM Gerber Files

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

Pedidos y calidad

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Serie de videos

Videos

Opciones de descarga

SCAC037 — CDC7005 SPI Software with Labview 8.0 Runtime Engine

Generadores de señal de reloj

Información de la versión