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Circuitos integrados LVDS, M-LVDS y PECL

DS90LT012AQ-Q1

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Receptor de línea diferencial LVDS para automoción

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DS90LT012AQ-Q1

ACTIVO
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Detalles del producto

Function Receiver Protocols CML, LVDS, LVPECL Number of transmitters 0 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 400 Input signal CML, LVDS, LVPECL Output signal CMOS Rating Automotive Operating temperature range (°C) -40 to 125
Function Receiver Protocols CML, LVDS, LVPECL Number of transmitters 0 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 400 Input signal CML, LVDS, LVPECL Output signal CMOS Rating Automotive Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8
  • AECQ-100 Grade 1
  • -40 to +125°C Temperature Range Operation
  • Compatible with ANSI TIA/EIA-644-A Standard
  • >400 Mbps (200 MHz) Switching Rates
  • 100 ps Differential Skew (Typical)
  • 3.5 ns Maximum Propagation Delay
  • Integrated Line Termination Resistor (100Ω Typical)
  • Single 3.3V power supply design
  • Power Down High Impedance on LVDS Inputs
  • LVDS Inputs Accept LVDS/CML/LVPECL Signals
  • Pinout Simplifies PCB Layout
  • Low Power Dissipation (10mW Typical@ 3.3V Static)
  • SOT-23 5-Lead Package

All trademarks are the property of their respective owners.

  • AECQ-100 Grade 1
  • -40 to +125°C Temperature Range Operation
  • Compatible with ANSI TIA/EIA-644-A Standard
  • >400 Mbps (200 MHz) Switching Rates
  • 100 ps Differential Skew (Typical)
  • 3.5 ns Maximum Propagation Delay
  • Integrated Line Termination Resistor (100Ω Typical)
  • Single 3.3V power supply design
  • Power Down High Impedance on LVDS Inputs
  • LVDS Inputs Accept LVDS/CML/LVPECL Signals
  • Pinout Simplifies PCB Layout
  • Low Power Dissipation (10mW Typical@ 3.3V Static)
  • SOT-23 5-Lead Package

All trademarks are the property of their respective owners.

The DS90LT012AQ is a single CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise, and high data rates. The devices are designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Swing (LVDS) technology

The DS90LT012AQ accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The DS90LT012AQ includes an input line termination resistor for point-to-point applications.

The DS90LT012AQ and companion LVDS line driver DS90LV011AQ provide a new alternative to high power PECL/ECL devices for high speed interface applications.

The DS90LT012AQ is a single CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise, and high data rates. The devices are designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Swing (LVDS) technology

The DS90LT012AQ accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The DS90LT012AQ includes an input line termination resistor for point-to-point applications.

The DS90LT012AQ and companion LVDS line driver DS90LV011AQ provide a new alternative to high power PECL/ECL devices for high speed interface applications.
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Documentación técnica

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Tipo Título Fecha
* Data sheet DS90LT012AQ Automotive LVDS Differential Line Receiver datasheet (Rev. E) 17 abr 2013
Application brief LVDS to Improve EMC in Motor Drives 27 sep 2018
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 03 ago 2018
Application note AN-1821 CPRI Repeater System (Rev. A) 26 abr 2013
Application note An Overview of LVDS Technology 05 oct 1998

Diseño y desarrollo

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Placa de evaluación

DS90LV047-48AEVM — Módulo de evaluación DS90LV047-48AEVM

The DS90LV047-48AEVM is an evaluation module (EVM) designed for performance and functional evaluation of Texas Instruments' DS90LV047A 3-V LVDS quad CMOS differential line driver and DS90LV048A 3-V LVDS CMOS differential line receiver. With this kit, users can quickly evaluate the output (...)
Guía del usuario: PDF
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Modelo de simulación

DS90LT012A IBIS Model

SNLM044.ZIP (11 KB) - IBIS Model
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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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Diseños de referencia

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Esquema: PDF
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This reference design demonstrates an efficient, low-noise five-rail power supply design for very high-speed Data Acquisition (DAQ) systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency-synchronized and phase-shifted in order to minimize input current ripple and (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

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This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is done by time interleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-010128 — Diseño de referencia de 20.8 GSPS escalable para digitalizadores de 12 bits

This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

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This reference design addresses synchronization design challenges associated with emerging 5G adapted applications like massive multiple input multiple output (mMIMO), phase array radar and communication payload. The typical RF front end contains antenna, low-noise amplifier (LNA), mixer, local (...)
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Esquema: PDF
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SOT-23 (DBV) 5 Ver opciones
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