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Circuitos integrados multicanal (PMIC)

TPS659037

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Administración de energía IC (PMIC) para procesadores ARM® Cortex™ A15

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TPS659037

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Detalles del producto

Processor supplier Texas Instruments Processor name Sitara AM57x Product type Processor and FPGA Regulated outputs (#) 14 Step-down DC/DC converter 7 Step-up DC/DC converter 0 LDO 7 Vin (min) (V) 3.135 Vin (max) (V) 5.25 Vout (min) (V) 0.7 Vout (max) (V) 3.3 Iout (max) (A) 6 Configurability Factory programmable, Software configurable Features Comm control, Power good, Power sequencing Rating Automotive, Catalog Operating temperature range (°C) -40 to 85 Step-down DC/DC controller 0 Step-up DC/DC controller 0 Iq (typ) (mA) 0.15 Switching frequency (max) (kHz) 2700 Shutdown current (ISD) (typ) (µA) 20 Switching frequency (typ) (kHz) 2200
Processor supplier Texas Instruments Processor name Sitara AM57x Product type Processor and FPGA Regulated outputs (#) 14 Step-down DC/DC converter 7 Step-up DC/DC converter 0 LDO 7 Vin (min) (V) 3.135 Vin (max) (V) 5.25 Vout (min) (V) 0.7 Vout (max) (V) 3.3 Iout (max) (A) 6 Configurability Factory programmable, Software configurable Features Comm control, Power good, Power sequencing Rating Automotive, Catalog Operating temperature range (°C) -40 to 85 Step-down DC/DC controller 0 Step-up DC/DC controller 0 Iq (typ) (mA) 0.15 Switching frequency (max) (kHz) 2700 Shutdown current (ISD) (typ) (µA) 20 Switching frequency (typ) (kHz) 2200
NFBGA (ZWS) 169 144 mm² 12 x 12
  • Seven Step-Down Switched-Mode Power Supply (SMPS) Regulators:
    • One 0.7 to 1.65 V at 6 A (10-mV Steps)
      • Dual-Phase Configuration With Digital Voltage Scaling (DVS) Control
    • One 0.7 to 1.65 V at 4 A (10-mV Steps)
      • Dual-Phase Configuration With DVS Control
    • One 0.7 to 3.3 V at 3 A (10 or 20-mV Steps)
      • Single-Phase Configuration
      • This Regulator can be Combined With the 6 A Resulting in a 9-A Triple-Phase Regulator (DVS Controlled)
    • Two 0.7 to 3.3 V at 2 A (10 or 20-mV Steps)
      • Single-Phase Configuration
      • One Regulator With DVS Control That can also be Configured as a 3-A Regulator
    • Two 0.7 to 3.3 V at 1 A (10 or 20-mV Steps)
      • Single-Phase Configuration
      • One Regulator With DVS Control
    • Output Current Measurement in All Except 1-A SMPS Regulators
    • Differential Remote Sensing (Output and Ground) in Dual-Phase and Triple-Phase Regulators
    • Hardware and Software-Controlled Eco-mode™ up to 5 mA with 15-µA Quiescent Current
    • Short-Circuit Protection
    • Powergood Indication (Voltage and Overcurrent Indication)
    • Internal Soft-Start for In-Rush Current Limitation
    • Ability to synchronize SMPS to External Clock or Internal Fallback Clock With Phase Synchronization
  • Seven General-Purpose Low Dropout Regulators (LDOs) with 50-mV Steps:
    • Two 0.9 to 3.3-V LDOs at 300 mA With Preregulated Supply
    • Two 0.9 to 3.3-V LDOs at 200 mA With Preregulated Supply
    • One 0.9 to 3.3-V LDOs at 50 mA With Preregulated Supply
    • One 100-mA USB LDO
    • One 0.9 to 3.3-V, Low-Noise LDO up to 100 mA (Low-Noise Performance up to 50 mA)
    • Two Additional LDOs for PMU Internal Use
    • Short-Circuit Protection
  • Clock Management 16-MHz Crystal Oscillator and 32-kHz RC Oscillator
    • One Buffered 32-kHz Output
  • Real-Time Clock (RTC) With Alarm Wake-Up Mechanism
  • 12-bit Sigma-Delta General-Purpose Analog-to-Digital-Converter (GPADC) With Three External Input Channels and Six Internal Channels for Self Monitoring
  • Thermal Monitoring
    • High Temperature Warning
    • Thermal Shutdown
  • Control
    • Configurable Power-Up and Power-Down Sequences (One-Time Programmable [OTP])
    • Configurable Sequences Between the SLEEP and ACTIVE States (OTP Programmable)
    • One Dedicated Digital Output Signal (REGEN) that can be Included in the Start-Up Sequence
    • Three Digital Output Signals MUXed With GPIO that can be Included in the Start-Up Sequence
    • Selectable Control Interface
      • One Serial Peripheral Interface (SPI) for Resource Configurations and DVS Control
      • Two I2C Interfaces. One Dedicated for DVS Control, and a General Purpose I2C Interface for Resource Configuration and DVS Control
  • Undervoltage Lockout
  • System Voltage Range from 3.135 to 5.25 V
  • Package Options
    • 12-mm × 12-mm 169-pin nFBGA with 0,8-mm Pin Pitch
  • Seven Step-Down Switched-Mode Power Supply (SMPS) Regulators:
    • One 0.7 to 1.65 V at 6 A (10-mV Steps)
      • Dual-Phase Configuration With Digital Voltage Scaling (DVS) Control
    • One 0.7 to 1.65 V at 4 A (10-mV Steps)
      • Dual-Phase Configuration With DVS Control
    • One 0.7 to 3.3 V at 3 A (10 or 20-mV Steps)
      • Single-Phase Configuration
      • This Regulator can be Combined With the 6 A Resulting in a 9-A Triple-Phase Regulator (DVS Controlled)
    • Two 0.7 to 3.3 V at 2 A (10 or 20-mV Steps)
      • Single-Phase Configuration
      • One Regulator With DVS Control That can also be Configured as a 3-A Regulator
    • Two 0.7 to 3.3 V at 1 A (10 or 20-mV Steps)
      • Single-Phase Configuration
      • One Regulator With DVS Control
    • Output Current Measurement in All Except 1-A SMPS Regulators
    • Differential Remote Sensing (Output and Ground) in Dual-Phase and Triple-Phase Regulators
    • Hardware and Software-Controlled Eco-mode™ up to 5 mA with 15-µA Quiescent Current
    • Short-Circuit Protection
    • Powergood Indication (Voltage and Overcurrent Indication)
    • Internal Soft-Start for In-Rush Current Limitation
    • Ability to synchronize SMPS to External Clock or Internal Fallback Clock With Phase Synchronization
  • Seven General-Purpose Low Dropout Regulators (LDOs) with 50-mV Steps:
    • Two 0.9 to 3.3-V LDOs at 300 mA With Preregulated Supply
    • Two 0.9 to 3.3-V LDOs at 200 mA With Preregulated Supply
    • One 0.9 to 3.3-V LDOs at 50 mA With Preregulated Supply
    • One 100-mA USB LDO
    • One 0.9 to 3.3-V, Low-Noise LDO up to 100 mA (Low-Noise Performance up to 50 mA)
    • Two Additional LDOs for PMU Internal Use
    • Short-Circuit Protection
  • Clock Management 16-MHz Crystal Oscillator and 32-kHz RC Oscillator
    • One Buffered 32-kHz Output
  • Real-Time Clock (RTC) With Alarm Wake-Up Mechanism
  • 12-bit Sigma-Delta General-Purpose Analog-to-Digital-Converter (GPADC) With Three External Input Channels and Six Internal Channels for Self Monitoring
  • Thermal Monitoring
    • High Temperature Warning
    • Thermal Shutdown
  • Control
    • Configurable Power-Up and Power-Down Sequences (One-Time Programmable [OTP])
    • Configurable Sequences Between the SLEEP and ACTIVE States (OTP Programmable)
    • One Dedicated Digital Output Signal (REGEN) that can be Included in the Start-Up Sequence
    • Three Digital Output Signals MUXed With GPIO that can be Included in the Start-Up Sequence
    • Selectable Control Interface
      • One Serial Peripheral Interface (SPI) for Resource Configurations and DVS Control
      • Two I2C Interfaces. One Dedicated for DVS Control, and a General Purpose I2C Interface for Resource Configuration and DVS Control
  • Undervoltage Lockout
  • System Voltage Range from 3.135 to 5.25 V
  • Package Options
    • 12-mm × 12-mm 169-pin nFBGA with 0,8-mm Pin Pitch

The TPS659037 device is an integrated power-management IC (PMIC). The device provides seven configurable step-down converters with up to 6 A of output current for memory, processor core, input-output (I/O), or preregulation of LDOs. One of these configurable step-down converters can be combined with another 3-A regulator to allow up to 9 A of output current. All of the step-down converters can synchronize to an external clock source between 1.7 MHz and 2.7 MHz, or an internal fallback clock at 2.2 MHz.

The TPS659037 device contains seven LDO regulators for external use. These LDO regulators can be supplied from either a system supply or a preregulated supply. The power-up and power-down controller is configurable and supports any power-up and power-down sequences (OTP based). The TPS659037 device includes a 32-kHz RC oscillator to sequence all resources during power up and power down. In cases where a fast start up is needed, a 16-MHz crystal oscillator is also included to quickly generate a stable 32-kHz for the system. All LDOs and SMPS converters can be controlled by the SPI or I2C interface, or by power request signals. In addition, voltage scaling registers allow transitioning the SMPS to different voltages by SPI, I2C, or roof and floor control.

One dedicated pin in each package can be configured as part of the power-up sequence to control external resources. General-purpose input-output (GPIO) functionality is available and two GPIOs can be configured as part of the power-up sequence to control external resources. Power request signals enable power mode control for power optimization. The device includes a general-purpose sigma-delta analog-to-digital converter (GPADC) with three external input channels.

The TPS659037 device is available in a 13-pin × 13-pin nFBGA package with a 0,8-mm pitch.

The TPS659037 device is an integrated power-management IC (PMIC). The device provides seven configurable step-down converters with up to 6 A of output current for memory, processor core, input-output (I/O), or preregulation of LDOs. One of these configurable step-down converters can be combined with another 3-A regulator to allow up to 9 A of output current. All of the step-down converters can synchronize to an external clock source between 1.7 MHz and 2.7 MHz, or an internal fallback clock at 2.2 MHz.

The TPS659037 device contains seven LDO regulators for external use. These LDO regulators can be supplied from either a system supply or a preregulated supply. The power-up and power-down controller is configurable and supports any power-up and power-down sequences (OTP based). The TPS659037 device includes a 32-kHz RC oscillator to sequence all resources during power up and power down. In cases where a fast start up is needed, a 16-MHz crystal oscillator is also included to quickly generate a stable 32-kHz for the system. All LDOs and SMPS converters can be controlled by the SPI or I2C interface, or by power request signals. In addition, voltage scaling registers allow transitioning the SMPS to different voltages by SPI, I2C, or roof and floor control.

One dedicated pin in each package can be configured as part of the power-up sequence to control external resources. General-purpose input-output (GPIO) functionality is available and two GPIOs can be configured as part of the power-up sequence to control external resources. Power request signals enable power mode control for power optimization. The device includes a general-purpose sigma-delta analog-to-digital converter (GPADC) with three external input channels.

The TPS659037 device is available in a 13-pin × 13-pin nFBGA package with a 0,8-mm pitch.
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Documentación técnica

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Tipo Título Fecha
* Data sheet TPS659037 Power management unit (PMU) for processor datasheet (Rev. G) PDF | HTML 20 ago 2018
* User guide TPS659037 Register Map (Rev. B) 12 feb 2019
Application note TPS659037 Design Checklist (Rev. B) 09 jun 2022
Application note POR Generation in TPS65903x, TPS65917-Q1, TPS65919-Q1, and TPS65916 Devices (Rev. A) 21 sep 2018
User guide TPS659037 user's guide to power AM574x, AM572x, and AM571x (Rev. F) 16 mar 2018
Application note Guide to Using the GPADC in TPS65903x, TPS65917-Q1, TPS65919-Q1, and TPS65916 de (Rev. A) 13 dic 2017
Technical article How to implement remote sense in your PMIC PDF | HTML 17 nov 2016
Technical article Using PMICs to support a wide range of power sequencing requirements PDF | HTML 01 nov 2016
Technical article Using TPS659037 to power the Sitara AM57x processors PDF | HTML 16 feb 2016
Application note TPS659037 Design Guide 21 sep 2015

Diseño y desarrollo

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Placa de evaluación

TPS659037EVM-090 — Módulo de evaluación TPS659037 de administración de energía IC

The TPS659037 device is an integrated power-management integrated circuit (PMIC) for industrial and consumer applications.  The device provides seven configurable step-down converters with up to 6A of output current for memory, processor core, input/output (I/O), or pre-regulation of LDOs. (...)

Guía del usuario: PDF
No disponible en TI.com
Placa de evaluación

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What is BeagleBone® AI?

Built on the proven BeagleBoard.org® open source Linux approach, BeagleBone® AI fills the gap between small SBCs and more powerful industrial computers. Based on the Texas Instruments, Sitara™ AM5729 processor, developers have access to a highly integrated and (...)

Desde: BeagleBoard.org Foundation
Guía del usuario: PDF
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Modelo de simulación

TPS659037 Unencrypted PSpice Transient Model Package (Rev. A)

SLIM334A.ZIP (591 KB) - PSpice Model
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Diseños de referencia

TIDEP0076 — Diseño de referencia de visión artificial 3D basado en el procesador AM572x con luz estructurada DLP

El diseño de visión artificial TIDEP0076 3D describe un escáner 3D integrado basado en el principio de luz estructurada. Una cámara digital junto con un procesador Sitara™ AM57xx System on Chip (SoC) se utiliza para capturar los patrones de luz reflejada de un proyector basado en DLP4500. El (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDEP0079 — Diseño de referencia EtherCAT® en Sitara AM57x Gb Ethernet y PRU-ICSS con envío activado por tiempo

El diseño de referencia TIDEP0079 demuestra una interfaz maestra EtherCAT® que se ejecuta en el procesador Sitara™ AM572x utilizando la pila EC-Master de acontis. Esta solución maestra EtherCAT se puede utilizar para aplicaciones de control de movimiento o PLC basadas en EtherCAT. El maestro (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-010010 — Diseño de referencia de PHY Gigabit Ethernet industrial

Las aplicaciones PLC requieren una interfaz gigabit Ethernet de alta velocidad. Esto se puede realizar mediante nuestro diseño de referencia que implementa el transceptor industrial DP83867IR gigabit Ethernet en el bloque periférico MAC Gigabit Ethernet dentro del procesador Sitara™ AM5728.
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDEP-0075 — Diseño de referencia maestro de puerta de enlace de comunicaciones industriales de PROFINET IRT a PR

PROFINET se está convirtiendo en el protocolo de Ethernet industrial líder en automatización debido a su alta velocidad, comunicaciones deterministas y conectividad empresarial. Sin embargo, como el bus de campo más popular del mundo, la importancia y el uso de PROFIBUS continuarán durante muchos (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDEP0074 — Diseño de referencia de motor de procesamiento de paquetes para reenvío de IEC61850 GOOSE

El diseño de referencia TIDEP0074 demuestra la lógica de conmutación y filtración de paquetes implementada en el núcleo M4 de AM572x basada en el Ethertype, dirección MAC e ID de aplicación (APPID) de los paquetes GOOSE recibidos del PRU-ICSS. Los paquetes se filtran y enrutan a destinos para (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDEP0078 — Diseño de referencia de servidor de acceso a datos OPC UA para AM572x

OPC UA es un protocolo industrial máquina a máquina diseñado para permitir la interoperabilidad y la comunicación entre todas las máquinas conectadas en la Industria 4.0. Este diseño de referencia demuestra el uso del kit de desarrollo (SDK) de servidor Matrikon OPC™ OPC UA para permitir las (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDEP0046 — Diseño de referencia de simulación Monte-Carlo en AM57x con OpenCL para aceleración DSP

TI’s high performance ARM® Cortex®-A15 based AM57x processors also integrate C66x DSPs. These DSPs were designed to handle high signal and data processing tasks that are often required by industrial, automotive and financial applications. The AM57x OpenCL implementation makes it easy (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDEP0047 — Diseño de referencia de las consideraciones sobre el diseño térmico y de energía con el procesador A

This is a reference design based on the AM57x processor and companion TPS659037 power management integrated circuit (PMIC).  This design specifically highlights important power and thermal design considerations and techniques for systems designed with AM57x and TPS659037.  It includes (...)
Design guide: PDF
Esquema: PDF
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NFBGA (ZWS) 169 Ultra Librarian
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