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TMS320DM8167

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DaVinci デジタル メディア プロセッサ

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TMS320DM8167

アクティブ
データシート ご注文はこちら

製品詳細

CPU 32-/64-bit Frequency (MHz) 1000 Display type 2 LCD PCIe 1 Operating system Android, DSP/BIOS, Linux Rating Catalog Operating temperature range (°C) -40 to 105
CPU 32-/64-bit Frequency (MHz) 1000 Display type 2 LCD PCIe 1 Operating system Android, DSP/BIOS, Linux Rating Catalog Operating temperature range (°C) -40 to 105
FCBGA (CYG) 1031 625 mm² 25 x 25
  • High-Performance DaVinci Digital Media Processors
    • ARM® Cortex-A8 RISC Processor
      • Up to 1.20 GHz
    • C674x VLIW DSP
      • Up to 1 GHz
      • Up to 8000 MIPS and 6000 MFLOPS
      • Fully Software-Compatible with C67x+ and C64x+
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • In-Order, Dual-Issue, Superscalar Processor Core
      • NEON Multimedia Architecture
    • Supports Integer and Floating Point (VFPv3-IEEE754 Compliant)
      • Jazelle RCT Execution Environment
  • ARM Cortex-A8 Memory Architecture
    • 32-KB Instruction and Data Caches
    • 256-KB L2 Cache
    • 64-KB RAM, 48-KB of Boot ROM
  • TMS320C674x Floating-Point VLIW DSP
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32-Bit and 40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision, 32-Bit) and DP (IEEE Double Precision, 64-Bit) Floating Point
      • Supports up to Four SP Adds Per Clock and Four DP Adds Every Two Clocks
      • Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating-Point Multiply Supported up to:
        • 2 SP x SP → SP Per Clock
        • 2 SP x SP → DP Every Two Clocks
        • 2 SP x DP → DP Every Three Clocks
        • 2 DP x DP → DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 x 32 Multiplies, Four 16 x 16-Bit Multiplies Including Complex Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle
  • C674x Two-Level Memory Architecture
    • 32-KB L1P and L1D RAM and Cache
    • 256-KB L2 Unified Mapped RAM and Caches
  • System Memory Management Unit (System MMU)
    • Maps C674x DSP and EMDA TCB Memory Accesses to System Addresses
  • 512KB of On-Chip Memory Controller (OCMC) RAM
  • Media Controller
    • Manages HDVPSS and HDVICP2 Modules
  • Up to Three Programmable High-Definition Video Image Coprocessing (HDVICP2) Engines
    • Encode, Decode, Transcode Operations
    • H.264, MPEG-2, VC-1, MPEG-4 SP and ASP
  • SGX530 3D Graphics Engine (Available Only on the DM8168 Device)
    • Delivers up to 30 MTriangles per Second
    • Universal Scalable Shader Engine
    • Direct3D Mobile, OpenGL ES 1.1 and 2.0, OpenVG 1.1, OpenMax API Support
    • Advanced Geometry DMA Driven Operation
    • Programmable HQ Image Anti-Aliasing
  • Endianness
    • ARM, DSP Instructions and Data – Little Endian
  • HD Video Processing Subsystem (HDVPSS)
    • Two 165-MHz HD Video Capture Channels
      • One 16-Bit or 24-Bit and One 16-Bit Channel
      • Each Channel Splittable Into Dual 8-Bit Capture Channels
    • Two 165-MHz HD Video Display Channels
      • One 16-Bit, 24-Bit, 30-Bit Channel and One 16-Bit Channel
    • Simultaneous SD and HD Analog Output
    • Digital HDMI 1.3 Transmitter with PHY with HDCP up to 165-MHz Pixel Clock
    • Three Graphics Layers
  • Dual 32-Bit DDR2 and DDR3 SDRAM Interfaces
    • Supports up to DDR2-800 and DDR3-1600
    • Up to Eight x8 Devices Total
    • 2GB of Total Address Space
    • Dynamic Memory Manager (DMM)
      • Programmable Multi-Zone Memory Mapping and Interleaving
      • Enables Efficient 2D Block Accesses
      • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
      • Optimizes Interlaced Accesses
  • One PCI Express (PCIe) 2.0 Port with Integrated PHY
    • Single Port with 1 or 2 Lanes at 5.0 GT per Second
    • Configurable as Root Complex or Endpoint
  • Serial ATA (SATA) 3.0 Gbps Controller with Integrated PHYs
    • Direct Interface for Two Hard Disk Drives
    • Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries
    • Supports Port Multiplier and Command-Based Switching
  • Two 10 Mbps, 100 Mbps, and 1000 Mbps Ethernet MACs (EMAC)
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • MII and GMII Media Independent Interfaces
    • Management Data I/O (MDIO) Module
  • Dual USB 2.0 Ports with Integrated PHYs
    • USB 2.0 High-Speed and Full-Speed Client
    • USB 2.0 High-Speed, Full-Speed, and Low-Speed Host
    • Supports Endpoints 0-15
  • General-Purpose Memory Controller (GPMC)
    • 8-Bit and 16-Bit Multiplexed Address and Data Bus
    • Up to 6 Chip Selects with up to 256-MB Address Space per Chip Select Pin
    • Glueless Interface to NOR Flash, NAND Flash (with BCH and Hamming Error Code Detection), SRAM and Pseudo-SRAM
    • Error Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit and 512-Byte Hardware ECC for NAND
    • Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs
  • Enhanced Direct-Memory-Access (EDMA) Controller
    • Four Transfer Controllers
    • 64 Independent DMA Channels and 8 Quick DMA (QDMA) Channels
  • Seven 32-Bit General-Purpose Timers
  • One System Watchdog Timer
  • Three Configurable UART, IrDA, and CIR Modules
    • UART0 with Modem Control Signals
    • Supports up to 3.6864 Mbps UART
    • SIR, MIR, FIR (4.0 MBAUD), and CIR
  • One 40-MHz Serial Peripheral Interface (SPI) with Four Chip Selects
  • SD and SDIO Serial Interface (1-Bit and 4-Bit)
  • Dual Inter-Integrated Circuit (I2C bus) Ports
  • Three Multichannel Audio Serial Ports (McASPs)
    • One Six-Serializer Transmit and Receive Port
    • Two Dual-Serializer Transmit and Receive Ports
    • DIT-Capable For SDIF and PDIF (All Ports)
  • Multichannel Buffered Serial Port (McBSP)
    • Transmit and Receive Clocks up to 48 MHz
    • Two Clock Zones and Two Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
  • Real-Time Clock (RTC)
    • One-Time or Periodic Interrupt Generation
  • Up to 64 General-Purpose I/O (GPIO) Pins
  • On-Chip ARM ROM Bootloader (RBL)
  • Power, Reset, and Clock Management
    • SmartReflex Technology (Level 2)
    • Seven Independent Core Power Domains
    • Clock Enable and Disable Control For Subsystems and Peripherals
  • IEEE 1149.1 (JTAG) and IEEE 1149.7 (cJTAG) Compatible
  • Via Channel Technology Enables use of
    0.8-mm Design Rules
  • 40-nm CMOS Technology
  • 3.3-V Single-Ended LVCMOS I/Os (Except for DDR3 at 1.5 V, DDR2 at 1.8 V, and DEV_CLKIN at 1.8 V)
  • High-Performance DaVinci Digital Media Processors
    • ARM® Cortex-A8 RISC Processor
      • Up to 1.20 GHz
    • C674x VLIW DSP
      • Up to 1 GHz
      • Up to 8000 MIPS and 6000 MFLOPS
      • Fully Software-Compatible with C67x+ and C64x+
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • In-Order, Dual-Issue, Superscalar Processor Core
      • NEON Multimedia Architecture
    • Supports Integer and Floating Point (VFPv3-IEEE754 Compliant)
      • Jazelle RCT Execution Environment
  • ARM Cortex-A8 Memory Architecture
    • 32-KB Instruction and Data Caches
    • 256-KB L2 Cache
    • 64-KB RAM, 48-KB of Boot ROM
  • TMS320C674x Floating-Point VLIW DSP
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32-Bit and 40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision, 32-Bit) and DP (IEEE Double Precision, 64-Bit) Floating Point
      • Supports up to Four SP Adds Per Clock and Four DP Adds Every Two Clocks
      • Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating-Point Multiply Supported up to:
        • 2 SP x SP → SP Per Clock
        • 2 SP x SP → DP Every Two Clocks
        • 2 SP x DP → DP Every Three Clocks
        • 2 DP x DP → DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 x 32 Multiplies, Four 16 x 16-Bit Multiplies Including Complex Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle
  • C674x Two-Level Memory Architecture
    • 32-KB L1P and L1D RAM and Cache
    • 256-KB L2 Unified Mapped RAM and Caches
  • System Memory Management Unit (System MMU)
    • Maps C674x DSP and EMDA TCB Memory Accesses to System Addresses
  • 512KB of On-Chip Memory Controller (OCMC) RAM
  • Media Controller
    • Manages HDVPSS and HDVICP2 Modules
  • Up to Three Programmable High-Definition Video Image Coprocessing (HDVICP2) Engines
    • Encode, Decode, Transcode Operations
    • H.264, MPEG-2, VC-1, MPEG-4 SP and ASP
  • SGX530 3D Graphics Engine (Available Only on the DM8168 Device)
    • Delivers up to 30 MTriangles per Second
    • Universal Scalable Shader Engine
    • Direct3D Mobile, OpenGL ES 1.1 and 2.0, OpenVG 1.1, OpenMax API Support
    • Advanced Geometry DMA Driven Operation
    • Programmable HQ Image Anti-Aliasing
  • Endianness
    • ARM, DSP Instructions and Data – Little Endian
  • HD Video Processing Subsystem (HDVPSS)
    • Two 165-MHz HD Video Capture Channels
      • One 16-Bit or 24-Bit and One 16-Bit Channel
      • Each Channel Splittable Into Dual 8-Bit Capture Channels
    • Two 165-MHz HD Video Display Channels
      • One 16-Bit, 24-Bit, 30-Bit Channel and One 16-Bit Channel
    • Simultaneous SD and HD Analog Output
    • Digital HDMI 1.3 Transmitter with PHY with HDCP up to 165-MHz Pixel Clock
    • Three Graphics Layers
  • Dual 32-Bit DDR2 and DDR3 SDRAM Interfaces
    • Supports up to DDR2-800 and DDR3-1600
    • Up to Eight x8 Devices Total
    • 2GB of Total Address Space
    • Dynamic Memory Manager (DMM)
      • Programmable Multi-Zone Memory Mapping and Interleaving
      • Enables Efficient 2D Block Accesses
      • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
      • Optimizes Interlaced Accesses
  • One PCI Express (PCIe) 2.0 Port with Integrated PHY
    • Single Port with 1 or 2 Lanes at 5.0 GT per Second
    • Configurable as Root Complex or Endpoint
  • Serial ATA (SATA) 3.0 Gbps Controller with Integrated PHYs
    • Direct Interface for Two Hard Disk Drives
    • Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries
    • Supports Port Multiplier and Command-Based Switching
  • Two 10 Mbps, 100 Mbps, and 1000 Mbps Ethernet MACs (EMAC)
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • MII and GMII Media Independent Interfaces
    • Management Data I/O (MDIO) Module
  • Dual USB 2.0 Ports with Integrated PHYs
    • USB 2.0 High-Speed and Full-Speed Client
    • USB 2.0 High-Speed, Full-Speed, and Low-Speed Host
    • Supports Endpoints 0-15
  • General-Purpose Memory Controller (GPMC)
    • 8-Bit and 16-Bit Multiplexed Address and Data Bus
    • Up to 6 Chip Selects with up to 256-MB Address Space per Chip Select Pin
    • Glueless Interface to NOR Flash, NAND Flash (with BCH and Hamming Error Code Detection), SRAM and Pseudo-SRAM
    • Error Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit and 512-Byte Hardware ECC for NAND
    • Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs
  • Enhanced Direct-Memory-Access (EDMA) Controller
    • Four Transfer Controllers
    • 64 Independent DMA Channels and 8 Quick DMA (QDMA) Channels
  • Seven 32-Bit General-Purpose Timers
  • One System Watchdog Timer
  • Three Configurable UART, IrDA, and CIR Modules
    • UART0 with Modem Control Signals
    • Supports up to 3.6864 Mbps UART
    • SIR, MIR, FIR (4.0 MBAUD), and CIR
  • One 40-MHz Serial Peripheral Interface (SPI) with Four Chip Selects
  • SD and SDIO Serial Interface (1-Bit and 4-Bit)
  • Dual Inter-Integrated Circuit (I2C bus) Ports
  • Three Multichannel Audio Serial Ports (McASPs)
    • One Six-Serializer Transmit and Receive Port
    • Two Dual-Serializer Transmit and Receive Ports
    • DIT-Capable For SDIF and PDIF (All Ports)
  • Multichannel Buffered Serial Port (McBSP)
    • Transmit and Receive Clocks up to 48 MHz
    • Two Clock Zones and Two Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
  • Real-Time Clock (RTC)
    • One-Time or Periodic Interrupt Generation
  • Up to 64 General-Purpose I/O (GPIO) Pins
  • On-Chip ARM ROM Bootloader (RBL)
  • Power, Reset, and Clock Management
    • SmartReflex Technology (Level 2)
    • Seven Independent Core Power Domains
    • Clock Enable and Disable Control For Subsystems and Peripherals
  • IEEE 1149.1 (JTAG) and IEEE 1149.7 (cJTAG) Compatible
  • Via Channel Technology Enables use of
    0.8-mm Design Rules
  • 40-nm CMOS Technology
  • 3.3-V Single-Ended LVCMOS I/Os (Except for DDR3 at 1.5 V, DDR2 at 1.8 V, and DEV_CLKIN at 1.8 V)

The DM816x DaVinci video processors are a highly integrated, programmable platform that leverages TI's DaVinci technology to meet the processing needs of the following applications: video encode, decode, transcode, and transrate; video security; video conferencing; video infrastructure; media server; and digital signage.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device combines programmable video and audio processing with a highly integrated peripheral set.

Key to the device are up to three high-definition video and imaging coprocessors (HDVICP2). Each coprocessor can perform a single 1080p60 H.264 encode or decode or multiple lower resolution or frame rate encodes and decodes. Multichannel HD-to-HD or HD-to-SD transcoding and multicoding are also possible. With the ability to simultaneously process 1080p60 streams, the TMS320DM816x device is a powerful solution for today's demanding HD video application requirements.

Programmability is provided by an ARM Cortex-A8 RISC CPU with NEON extension, TI C674x VLIW floating-point DSP core, and high-definition video and imaging coprocessors. The ARM processor lets developers keep control functions separate from audio and video algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-bit RISC processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache; 256KB of L2 cache; 48KB of public ROM, and 64KB of RAM.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD video processing subsystem (HDVPSS), which provides output of simultaneous HD and SD analog video and dual HD video inputs; up to two Gigabit Ethernet MACs (10 Mbps,100, Mbps, 1000 Mbps) with GMII and MDIO interface; two USB ports with integrated 2.0 PHY; PCIe port x2 lanes GEN2 compliant interface, which allows the device to act as a PCIe root complex or device endpoint; one 6-channel McASP audio serial port (with DIT mode); two dual-channel McASP audio serial ports (with DIT mode); one McBSP multichannel buffered serial port; three UARTs with IrDA and CIR support; SPI serial interface; SD and SDIO serial interface; two I2C master and slave interfaces; up to 64 GPIO pins; seven 32-bit timers; system watchdog timer; dual DDR2 and DDR3 SDRAM interface; flexible 8-bit and 16-bit asynchronous memory interface; and up to two SATA interfaces for external storage on two disk drives or more with the use of a port multiplier.

The device also includes an SGX530 3D graphics engine (available only on the TMS320DM8168 device) to enable sophisticated GUIs and compelling user interfaces and interactions. Additionally, the device has a complete set of development tools for both the ARM and DSP, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Microsoft Windows debugger interface for visibility into source code execution.

The C674x DSP core is the high-performance floating-point DSP generation in the TMS320C6000 DSP platform. The C674x floating-point DSP processor uses 32KB of L1 program memory and 32KB of L1 data memory. Up to 32KB of L1P can be configured as program cache. The remaining is noncacheable no-wait-state program memory. Up to 32KB of L1D can be configured as data cache. The remaining is noncacheable no-wait-state data memory. The DSP has 256KB of L2 RAM, which can be defined as SRAM, L2 cache, or a combination of both. All C674x L3 and off-chip memory accesses are routed through a system MMU.

The device package has been specially engineered with Via Channel technology. This technology allows use of 0.8-mm pitch PCB feature sizes in this 0.65-mm pitch package, and substantially reduces PCB costs. Via Channel technology also allows PCB routing in only two signal layers due to the increased layer efficiency of the Via Channel BGA technology.

The DM816x DaVinci video processors are a highly integrated, programmable platform that leverages TI's DaVinci technology to meet the processing needs of the following applications: video encode, decode, transcode, and transrate; video security; video conferencing; video infrastructure; media server; and digital signage.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device combines programmable video and audio processing with a highly integrated peripheral set.

Key to the device are up to three high-definition video and imaging coprocessors (HDVICP2). Each coprocessor can perform a single 1080p60 H.264 encode or decode or multiple lower resolution or frame rate encodes and decodes. Multichannel HD-to-HD or HD-to-SD transcoding and multicoding are also possible. With the ability to simultaneously process 1080p60 streams, the TMS320DM816x device is a powerful solution for today's demanding HD video application requirements.

Programmability is provided by an ARM Cortex-A8 RISC CPU with NEON extension, TI C674x VLIW floating-point DSP core, and high-definition video and imaging coprocessors. The ARM processor lets developers keep control functions separate from audio and video algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-bit RISC processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache; 256KB of L2 cache; 48KB of public ROM, and 64KB of RAM.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD video processing subsystem (HDVPSS), which provides output of simultaneous HD and SD analog video and dual HD video inputs; up to two Gigabit Ethernet MACs (10 Mbps,100, Mbps, 1000 Mbps) with GMII and MDIO interface; two USB ports with integrated 2.0 PHY; PCIe port x2 lanes GEN2 compliant interface, which allows the device to act as a PCIe root complex or device endpoint; one 6-channel McASP audio serial port (with DIT mode); two dual-channel McASP audio serial ports (with DIT mode); one McBSP multichannel buffered serial port; three UARTs with IrDA and CIR support; SPI serial interface; SD and SDIO serial interface; two I2C master and slave interfaces; up to 64 GPIO pins; seven 32-bit timers; system watchdog timer; dual DDR2 and DDR3 SDRAM interface; flexible 8-bit and 16-bit asynchronous memory interface; and up to two SATA interfaces for external storage on two disk drives or more with the use of a port multiplier.

The device also includes an SGX530 3D graphics engine (available only on the TMS320DM8168 device) to enable sophisticated GUIs and compelling user interfaces and interactions. Additionally, the device has a complete set of development tools for both the ARM and DSP, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Microsoft Windows debugger interface for visibility into source code execution.

The C674x DSP core is the high-performance floating-point DSP generation in the TMS320C6000 DSP platform. The C674x floating-point DSP processor uses 32KB of L1 program memory and 32KB of L1 data memory. Up to 32KB of L1P can be configured as program cache. The remaining is noncacheable no-wait-state program memory. Up to 32KB of L1D can be configured as data cache. The remaining is noncacheable no-wait-state data memory. The DSP has 256KB of L2 RAM, which can be defined as SRAM, L2 cache, or a combination of both. All C674x L3 and off-chip memory accesses are routed through a system MMU.

The device package has been specially engineered with Via Channel technology. This technology allows use of 0.8-mm pitch PCB feature sizes in this 0.65-mm pitch package, and substantially reduces PCB costs. Via Channel technology also allows PCB routing in only two signal layers due to the increased layer efficiency of the Via Channel BGA technology.
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技術資料

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上位の文書 タイプ タイトル フォーマットオプション 最新の英語版をダウンロード 日付
* データシート TMS320DM816x DaVinci Digital Media Processors データシート (Rev. F) PDF | HTML 2015年 3月 17日
* エラッタ TMS320DM816x DaVinci Digital Media Processors Silicon Errata (Rev 2.1 & Earlier) (Rev. F) 2015年 3月 17日
* ユーザー・ガイド TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (Rev. C) 2015年 3月 19日
アプリケーション・ノート High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023年 2月 24日
アプリケーション・ノート DM816xx Easy CYG Package PCB Escape Routing (Rev. A) 2015年 3月 19日
ユーザー・ガイド TMS320DM816x DaVinci Video Processors Technical Reference Manual (Rev. B) 2013年 3月 26日
その他の技術資料 DM81x Design Network Partners 2012年 6月 5日
アプリケーション・ノート Introduction to TMS320C6000 DSP Optimization 2011年 10月 6日
アプリケーション・ノート TMS320DM816x/TMS320C6A816x/AM389x Power Estimation Spreadsheet 2011年 5月 18日
アプリケーション・ノート PCIe to USB on the TMS320DM816x/TMS320C6A816x/AM389x Evaluation Board 2011年 3月 1日
製品概要 Software Makes Development Easy for DM8168 and DM8148 2011年 3月 1日
アプリケーション・ノート TMS320DM816x/C6A816x/AM389x DDR3 Initialization With Software Leveling 2011年 3月 1日
製品概要 Video Analytics on TI's Davinci Digital Media Processors Backgrounder 2011年 3月 1日
ユーザー・ガイド TMS320C674x DSP CPU and Instruction Set User's Guide (Rev. B) 2010年 7月 30日

設計と開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。

評価ボード

Z3-3P-VIDEO-EVMS — Z3 Technology 社プロセッサ・ビデオの評価モジュール

Z3 は、TI の DaVinci および AM57x プロセッサにフォーカスしオープンソース・ソフトウェア・アーキテクチャの開発、サポートを行います。取り扱い製品には、マルチメディア向けのフレームワーク、周辺装置ドライバ、製造モジュール、および包括的な製品設計サービスが含まれます。さらに Z3 は、システム・レベル設計と、有線およびワイヤレスの両方のメディア製品も提供します。

Z3 Technology の詳細については、http://z3technology.com でご確認ください。
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すべての XDS デバッグ・プローブは、組み込みトレース・バッファ (ETB) を搭載しているすべての ARM プロセッサと DSP プロセッサで、コア・トレースとシステム・トレースをサポートしています。ピン経由でコア・トレースを実行する場合、XDS560v2 PRO TRACE が必要です。

(...)

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デバッグ・プローブ

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 システム・トレース USB およびイーサネット

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

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デバッグ・プローブ

LB-3P-TRACE32-DSP — デジタル信号プロセッサ（DSP）用 Lauterbach TRACE32デバッグおよびトレースシステム

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

購入先：Lauterbach GmbH
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ソフトウェア開発キット (SDK)

LINUXEZSDK-DAVINCI — Linux EZ ソフトウェア開発キット（EZSDK）、DM814x および DM816x 向け - ALPHA

The Linux EZ Software Development Kit (EZ SDK) allows customers to evaluate their devices in minutes and begin development in less than an hour. This kit provides everything DaVinci™ developers need to evaluate and start developing on the DaVinci™ DM816x/DM814x processors. With the (...)

サポート対象の製品とハードウェア

サポート対象の製品とハードウェア
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ドライバまたはライブラリ

SPRC264 — TMS320C5000/6000 イメージ ライブラリ（IMGLIB）

C5000/6000 画像処理ライブラリ（IMGLIB）は、C言語プログラマ向けの最適化された画像/ビデオ処理関数ライブラリです。これは、計算負荷の高いリアルタイム アプリケーションで通常使用される、C言語から呼び出し可能な汎用の画像/動画処理ルーチンを含んでいます。これらのルーチンを使用することで、同等の標準ANSI C言語コードよりも高いパフォーマンスを実現できます。IMGLIBは、すぐに使えるDSP関数をソースコード付きで提供することで、アプリケーション開発期間を大幅に短縮できます。


ベンチマークを参照してください：各DSP コアのベンチマーク

ユーザー ガイド: PDF
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ドライバまたはライブラリ

SPRC265 — TMS320C6000 DSP ライブラリ（DSPLIB）

TMS320C6000 Digital Signal Processor Library (DSPLIB) は、Cプログラマー向けのプラットフォーム最適化DSP関数ライブラリです。これは、計算集約的なリアルタイム アプリケーションで一般的に使用される、C言語から呼び出し可能な汎用信号処理ルーチンを含んでいます。これらのルーチンを使用することで、同等の標準ANSI C言語コードよりも高いパフォーマンスを実現できます。DSPLIBは、すぐに使えるDSP関数をソースコード付きで提供することで、アプリケーション開発期間を大幅に短縮できます。


ベンチマークを参照してください：各DSP コアのベンチマーク

ユーザー ガイド: PDF
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シミュレーション・モデル

DM816x CYG PG1x BSDL Model (Rev. A)

SPRM521A.ZIP (23 KB) - BSDL Model
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シミュレーション・モデル

DM816x CYG PG2x BSDL Model

SPRM569.ZIP (23 KB) - BSDL Model
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パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
FCBGA (CYG) 1031 Ultra Librarian
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購入と品質

記載されている情報：
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  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
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  • アセンブリ拠点

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