제품 상세 정보

Sample rate (max) (Msps) 155 Resolution (Bits) 14 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 1100 Features High Performance Rating Space Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 967 Architecture Pipeline SNR (dB) 70.1 ENOB (bit) 11.3 SFDR (dB) 82.3 Operating temperature range (°C) -55 to 125 Input buffer No Radiation, TID (typ) (krad) 100 Radiation, SEL (MeV·cm2/mg) 120
Sample rate (max) (Msps) 155 Resolution (Bits) 14 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 1100 Features High Performance Rating Space Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 967 Architecture Pipeline SNR (dB) 70.1 ENOB (bit) 11.3 SFDR (dB) 82.3 Operating temperature range (°C) -55 to 125 Input buffer No Radiation, TID (typ) (krad) 100 Radiation, SEL (MeV·cm2/mg) 120
CFP (NBA) 48 132.25 mm² 11.5 x 11.5
  • 5962R0626201VXC
    • Total Ionizing Dose (TID) 100 krad(Si)
    • Single Event Latch-up 120 MeV-cm2/mg
      (See Radiation Reports)
  • 1.1-GHz Full-Power Bandwidth
  • Internal Sample-and-Hold Circuit
  • Low-Power Consumption
  • Internal Precision 1-V Reference
  • Single-Ended or Differential Clock Modes
  • Data Ready Output Clock
  • Clock Duty Cycle Stabilizer
  • Dual 3.3-V and 1.8-V Supply Operation (±10%)
  • Power-Down Mode
  • Offset Binary or 2’s Complement Output Data Format
  • 48-pin CFP Package (11.5-mm × 11.5-mm, 0.635-mm Pin-Pitch)
  • Key Specifications
    • Resolution 14 Bits
    • Conversion Rate 155 MSPS
    • SNR (fIN = 70 MHz) 70.1 dBFS (typ)
    • SFDR (fIN = 70 MHz) 82.3 dBFS (typ)
    • ENOB (fIN = 70 MHz) 11.3 Bits (typ)
    • Full-Power Bandwidth 1.1 GHz (typ)
    • Power Consumption 967 mW (typ)
  • 5962R0626201VXC
    • Total Ionizing Dose (TID) 100 krad(Si)
    • Single Event Latch-up 120 MeV-cm2/mg
      (See Radiation Reports)
  • 1.1-GHz Full-Power Bandwidth
  • Internal Sample-and-Hold Circuit
  • Low-Power Consumption
  • Internal Precision 1-V Reference
  • Single-Ended or Differential Clock Modes
  • Data Ready Output Clock
  • Clock Duty Cycle Stabilizer
  • Dual 3.3-V and 1.8-V Supply Operation (±10%)
  • Power-Down Mode
  • Offset Binary or 2’s Complement Output Data Format
  • 48-pin CFP Package (11.5-mm × 11.5-mm, 0.635-mm Pin-Pitch)
  • Key Specifications
    • Resolution 14 Bits
    • Conversion Rate 155 MSPS
    • SNR (fIN = 70 MHz) 70.1 dBFS (typ)
    • SFDR (fIN = 70 MHz) 82.3 dBFS (typ)
    • ENOB (fIN = 70 MHz) 11.3 Bits (typ)
    • Full-Power Bandwidth 1.1 GHz (typ)
    • Power Consumption 967 mW (typ)

The ADC14155QML-SP is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 14-bit digital words at rates up to 155 MSPS. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC14155 operates from dual 3.3-V and 1.8-V power supplies and consumes 967 mW of power at 155 MSPS.

The separate 1.8-V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 5 mW with the clock input disabled, while still allowing fast wake-up time to full operation. The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1-V internal voltage reference is provided, or the ADC14155 can be operated with an external reference. The Clock mode (differential versus single-ended) and output data format (offset binary versus 2’s complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of clock duty cycles.

The ADC14155QML-SP is available in a 48-lead thermally enhanced multi-layer ceramic quad package and operates over the military temperature range of –55°C to +125°C.

The ADC14155QML-SP is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 14-bit digital words at rates up to 155 MSPS. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC14155 operates from dual 3.3-V and 1.8-V power supplies and consumes 967 mW of power at 155 MSPS.

The separate 1.8-V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 5 mW with the clock input disabled, while still allowing fast wake-up time to full operation. The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1-V internal voltage reference is provided, or the ADC14155 can be operated with an external reference. The Clock mode (differential versus single-ended) and output data format (offset binary versus 2’s complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of clock duty cycles.

The ADC14155QML-SP is available in a 48-lead thermally enhanced multi-layer ceramic quad package and operates over the military temperature range of –55°C to +125°C.

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모두 보기14
유형 직함 날짜
* Data sheet ADC14155QML-SP, radiation hardened, 14-Bit, 155-MSPS, 1.1-GHz bandwidth A/D converter datasheet (Rev. L) PDF | HTML 2019/02/13
* SMD ADC14155QML-SP SMD 5962-06262 2018/05/29
* Radiation & reliability report ADC141555W-MLS, DAC121S101WGRQV, ADC08D1000WGFQV TID Report 2012/05/07
* Radiation & reliability report ADC14155W-MLS SEL Report 2012/05/07
* Radiation & reliability report ADC14155W-MLS SEU Report 2012/05/07
* Radiation & reliability report ADC14155W-MLS TID Report 2012/05/07
* Radiation & reliability report Analysis of Low Dose Rate Effects on Parasitic Bipolar Structures in CMOS Proces 2012/05/04
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) 2023/08/31
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A) PDF | HTML 2022/11/17
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022/10/19
Selection guide TI Space Products (Rev. I) 2022/03/03
E-book Radiation Handbook for Electronics (Rev. A) 2019/05/21
Application note AN-1718 Differential Amplifier Applications Up to 400 MHz (Rev. B) 2013/05/01
User guide ADC14155: 14-Bit, 155 MSPS Analog to Digital Converter User Guide 2012/02/21

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WaveVision 4 software is part of the WaveVision system that includes the WaveVision Data Capture Board. The WaveVision system an easy-to-use data acquisition and analysis tool, designed to help you evaluate TI's analog-to-digital and digital-to-analog converter products. Used in conjunction with (...)
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ADC14155QML IBIS Model

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TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
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