DAC12DL3200
- 12-bit resolution
- Maximum input and output sample rate:
- Single channel up to 6.4 GSPS
- Dual channel up to 3.2 GSPS
- Multi-Nyquist operating modes:
- Single channel modes: NRZ, RTZ, RF
- Dual channel modes: NRZ, RTZ, RF, 2xRF
- Low latency through device: 6 to 8 ns
- Matching transmit capabilities to the low latency receiver ADC12DL3200
- DAC and ADC combined latency < 15 ns (not including FPGA)
- Parallel DDR LVDS interface:
- Source synchronous interface to simplify timing:
- 24 or 48 LVDS pairs up to 1.6 Gbps
- 1 LVDS DDR clock per 12-bit bus
- Output frequency range: > 8 GHz
- Full-scale current: 21 mA
- Simplified clocking and synchronization
- SYSREF windowing eases setup and hold times
- On-chip direct digital synthesizer (DDS)
- Single-tone and two-tone sine wave generation
- 32 x 32-bit numerically controlled oscillators
- Fast frequency hopping capability (< 500 ns)
- Synchronous CMOS frequency/phase input
- Performance at fOUT = 4.703 GHz, 6.4 GSPS, RF mode
- Output power: –3 dBm
- Noise floor (70 MHz offset): –147 dBc/Hz
- SFDR: 60 dBc
- Power supplies: 1.0 V, 1.8 V, –1.8 V
- Power consumption: 1.49 W (2-ch, RF mode, 3.2 GSPS)
- Package: 256-Ball FCBGA (17x17 mm, 1 mm pitch)
The DAC12DL3200 is a very low latency, dual channel, RF sampling digital-to-analog converter (DAC) capable of input and output rates of up to 3.2-GSPS in dual channel mode or 6.4-GSPS in single channel mode. The DAC can transmit signal bandwidths beyond 2 GHz at carrier frequencies approaching 8 GHz when using the multi-Nyquist output modes. The high output frequency range enables direct sampling through C-band (8 GHz) and beyond.
The DAC12DL3200 can be used as an I/Q baseband DAC in dual channel mode. The high sampling rate and output frequency range also makes the DAC12DL3200 capable of arbitrary waveform generation (AWG) and direct digital synthesis (DDS). An integrated DDS block enables single tone and two tone generation on chip.
The DAC12DL3200 has a parallel LVDS interface that consists of up to 48 LVDS pairs and 4 DDR LVDS clocks. A strobe signal is used to synchronize the interface which can be sent over the least significant bit (LSB) or optionally over dedicated strobe LVDS lanes. Each LVDS pair is capable of up to 1.6 Gbps. Multi-device synchronization is supported using a synchronization signal (SYSREF) and is compatible with JESD204B/C clocking devices. SYSREF windowing eases synchronization in multi-device systems.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | DAC12DL3200 up to 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel 12-bit Digital-to-Analog Converter (DAC) with Low-Latency LVDS Interface datasheet (Rev. B) | PDF | HTML | 2022. 6. 27 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
DAC12DL3200EVM — 12비트, 듀얼 3.2GSPS 또는 단일 6.4GSPS, RF 샘플링 DAC용 DAC12DL3200 평가 모듈
DAC12DL3200 평가 모듈(EVM)은 초저 지연 듀얼 채널 12비트 RF 샘플링 디지털-아날로그 변환기(DAC)로 듀얼 채널 모드에서 최대 샘플링 속도 3.2GSPS, 단일 채널 모드에서 6.4GSPS까지 작동 가능한 DAC12DL3200 평가용 플랫폼입니다.
DAC12DL3200은 다중 Nyquist 모드를 사용하는 경우 8GHz에 가까운 반송 주파수에서 2GHz를 초과하는 신호 대역폭을 전송할 수 있습니다. DAC12DL3200EVM 장치 입력 데이터는 고속 저전압 차동 신호(LVDS) 인터페이스를 통해 전송됩니다.
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| FCBGA (ACF) | 256 | Ultra Librarian |
| FCBGA (ALJ) | 256 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.