홈 로직 및 전압 변환 버퍼, 드라이버 및 트랜시버 비인버팅 버퍼 및 드라이버
홈
로직 및 전압 변환
버퍼, 드라이버 및 트랜시버
비인버팅 버퍼 및 드라이버

SN54LVC541A

활성

3상 출력을 지원하는 군사용 8채널, 2V~3.6V 버퍼

지금 주문하기
데이터 시트

SN54LVC541A

활성
데이터 시트 지금 주문하기

제품 상세 정보

Technology family LVC Supply voltage (min) (V) 2 Supply voltage (max) (V) 3.6 Number of channels 8 IOL (max) (mA) 24 Supply current (max) (µA) 10 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Military Operating temperature range (°C) -55 to 125
Technology family LVC Supply voltage (min) (V) 2 Supply voltage (max) (V) 3.6 Number of channels 8 IOL (max) (mA) 24 Supply current (max) (µA) 10 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Military Operating temperature range (°C) -55 to 125
CDIP (J) 20 167.464 mm² 24.2 x 6.92 CFP (W) 20 90.5828 mm² 13.09 x 6.92 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Operates from 1.65V to 3.6V
  • Inputs accept voltages to 5.5V
  • Maximum tpd of 5.1ns at 3.3V
  • Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) >2V at VCC = 3.3V, TA = 25°C
  • Support mixed-mode signal operation on all ports (5V input/output voltage with 3.3V VCC)
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Latch-up performance exceeds 100mA per JESD 78
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted, on all other products, production processing does not necessarily include testing of all parameters
  • Operates from 1.65V to 3.6V
  • Inputs accept voltages to 5.5V
  • Maximum tpd of 5.1ns at 3.3V
  • Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) >2V at VCC = 3.3V, TA = 25°C
  • Support mixed-mode signal operation on all ports (5V input/output voltage with 3.3V VCC)
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Latch-up performance exceeds 100mA per JESD 78
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted, on all other products, production processing does not necessarily include testing of all parameters

The SNx4LVC541A contains eight non-inverting buffers with 3-state outputs. The active low output enable pins (OE1 and OE2) control all eight channels, and are configured so that both must be low for the outputs to be active.

The SNx4LVC541A contains eight non-inverting buffers with 3-state outputs. The active low output enable pins (OE1 and OE2) control all eight channels, and are configured so that both must be low for the outputs to be active.
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기술 자료

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28개 모두 보기
상위 문서 유형 직함 형식 옵션 날짜
* Data sheet SNx4LVC541A Octal Buffers/Drivers With 3-State Outputs datasheet (Rev. O) PDF | HTML 2026/06/25
* SMD SN54LVC541A SMD 5962-97595 2016/06/21
Selection guide Logic Guide (Rev. AC) PDF | HTML 2025/11/13
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Little Logic Guide 2018 (Rev. G) 2018/07/06
Application note How to Select Little Logic (Rev. A) 2016/07/26
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004/11/04
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 2003/11/06
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 2002/12/18
Application note Texas Instruments Little Logic Application Report 2002/11/01
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002/05/10
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002/03/27
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997/12/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note LVC Characterization Information 1996/12/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Design guide Low-Voltage Logic (LVC) Designer's Guide 1996/09/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01

설계 및 개발

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패키지 핀 CAD 기호, 풋프린트 및 3D 모델
CDIP (J) 20 Ultra Librarian
CFP (W) 20 Ultra Librarian
LCCC (FK) 20 Ultra Librarian
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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