SN74ABT162827A

활성

TTL 호환 CMOS 입력 및 3상 출력을 지원하는 20채널 4.5V~5.5V 버퍼

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document-pdfAcrobat SN54ABT162827A, SN74ABT162827A datasheet (Rev. F) (영어)

SN74ABT162827A

활성

데이터 시트

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제품 상세 정보

Technology family

ABT

Number of channels

20

IOL (max) (mA)

12

Supply current (max) (µA)

32000

IOH (max) (mA)

-12

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Balanced outputs, Damping resistors, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

ABT

Number of channels

20

IOL (max) (mA)

12

Supply current (max) (µA)

32000

IOH (max) (mA)

-12

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Balanced outputs, Damping resistors, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SSOP (DL)

56

190.647 mm² (18.42 mm × 10.35 mm)

TSSOP (DGG)

56

113.4 mm² (14 mm × 8.1 mm)

Members of the Texas Instruments Widebus™ Family
Output Ports Have Equivalent 25- Series Resistors, So No External Resistors Are Required
High-Impedance State During Power Up and Power Down
Typical V_OLP (Output Ground Bounce)
< 1 V at V_CC= 5 V, T_A = 25°C
Distributed V_CC and GND Pin Minimizes High-Speed Switching Noise
I_off and Power-Up 3-State Support Hot Insertion
Flow-Through Architecture Optimizes PCB Layout
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

Widebus is a trademark of Texas Instruments.

Members of the Texas Instruments Widebus™ Family
Output Ports Have Equivalent 25- Series Resistors, So No External Resistors Are Required
High-Impedance State During Power Up and Power Down
Typical V_OLP (Output Ground Bounce)
< 1 V at V_CC= 5 V, T_A = 25°C
Distributed V_CC and GND Pin Minimizes High-Speed Switching Noise
I_off and Power-Up 3-State Support Hot Insertion
Flow-Through Architecture Optimizes PCB Layout
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

Widebus is a trademark of Texas Instruments.

The ’ABT162827A devices are noninverting 20-bit buffers composed of two 10-bit buffers with separate output-enable signals. For either 10-bit buffer, the two output-enable (1OE1\ and 1OE2\, or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer are in the high-impedance state.

The outputs, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

To ensure the high-impedance state during power up or power down, OE\ shall be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The ’ABT162827A devices are noninverting 20-bit buffers composed of two 10-bit buffers with separate output-enable signals. For either 10-bit buffer, the two output-enable (1OE1\ and 1OE2\, or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer are in the high-impedance state.

The outputs, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

To ensure the high-impedance state during power up or power down, OE\ shall be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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