홈 로직 및 전압 변환 버퍼, 드라이버 및 트랜시버 범용 트랜시버
홈
로직 및 전압 변환
버퍼, 드라이버 및 트랜시버
범용 트랜시버

SN74ALVCH16901

활성

패리티 생성기/검사기를 지원하는 18비트 범용 버스 트랜시버

지금 주문
데이터 시트

SN74ALVCH16901

활성
데이터 시트 지금 주문

제품 상세 정보

Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 18 IOL (max) (mA) 24 IOH (max) (mA) -32 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Positive input clamp diode, Ultra high speed (tpd <5ns) Technology family ALVC Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 18 IOL (max) (mA) 24 IOH (max) (mA) -32 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Positive input clamp diode, Ultra high speed (tpd <5ns) Technology family ALVC Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 64 137.7 mm² 17 x 8.1
  • Member of the Texas Instruments Widebus+™ Family
  • UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
  • Operates From 1.65 V to 3.6 V
  • Max tpd of 4.4 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Simultaneously Generates and Checks Parity
  • Option to Select Generate Parity and Check or Feed-Through Data/Parity in A-to-B or B-to-A Directions
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Widebus+ and UBT are trademarks of Texas Instruments Incorporated.
  • Member of the Texas Instruments Widebus+™ Family
  • UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
  • Operates From 1.65 V to 3.6 V
  • Max tpd of 4.4 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Simultaneously Generates and Checks Parity
  • Option to Select Generate Parity and Check or Feed-Through Data/Parity in A-to-B or B-to-A Directions
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Widebus+ and UBT are trademarks of Texas Instruments Incorporated.

This 18-bit (dual-octal) noninverting registered transceiver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction.

The SN74ALVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock-enable (CLKENAB\ or CLKENBA\) inputs. It also provides parity-enable (SEL\) and parity-select (ODD/EVEN\) inputs and separate error-signal (ERRA\ or ERRB\) outputs for checking parity. The direction of data flow is controlled by OEAB\ and OEBA\. When SEL\ is low, the parity functions are enabled. When SEL\ is high, the parity functions are disabled and the device acts as an 18-bit registered transceiver.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The A and B I/Os and APAR and BPAR inputs have bus-hold circuitry. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This 18-bit (dual-octal) noninverting registered transceiver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction.

The SN74ALVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock-enable (CLKENAB\ or CLKENBA\) inputs. It also provides parity-enable (SEL\) and parity-select (ODD/EVEN\) inputs and separate error-signal (ERRA\ or ERRB\) outputs for checking parity. The direction of data flow is controlled by OEAB\ and OEBA\. When SEL\ is low, the parity functions are enabled. When SEL\ is high, the parity functions are disabled and the device acts as an 18-bit registered transceiver.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The A and B I/Os and APAR and BPAR inputs have bus-hold circuitry. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
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기술 자료

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19개 모두 보기
유형 직함 날짜
* Data sheet SN74ALVCH16901 datasheet (Rev. F) 2004/08/20
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018/09/17
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
User guide ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) 2002/08/01
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 1999/09/08
Application note TI SN74ALVC16835 Component Specification Analysis for PC100 1998/08/03
Application note Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) 1998/05/13
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997/12/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01
Selection guide Logic Guide (Rev. AC) PDF | HTML 1994/06/01

설계 및 개발

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시뮬레이션 모델

SN74ALVCH16901 IBIS Model (Rev. A)

SCEM041A.ZIP (7 KB) - IBIS Model
다운로드
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
TSSOP (DGG) 64 Ultra Librarian
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
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  • 조립 위치

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