SN74LV8151

Name: SN74LV8151
Brand: TI
SKU: SN74LV8151
Price: 0.503 USD

활성

TTL 호환 CMOS 입력을 지원하는 10채널, 2V~5.5V 버퍼

지금 주문

데이터 시트

document-pdfAcrobat SN74LV8151 datasheet (영어)

SN74LV8151

활성

데이터 시트

지금 주문

제품 상세 정보

Technology family

LV-A

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Number of channels

10

IOL (max) (mA)

12

Supply current (max) (µA)

20

IOH (max) (mA)

-12

Input type

Schmitt-Trigger

Output type

3-State

Features

Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

LV-A

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Number of channels

10

IOL (max) (mA)

12

Supply current (max) (µA)

20

IOH (max) (mA)

-12

Input type

Schmitt-Trigger

Output type

3-State

Features

Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SOIC (DW)

24

159.65 mm² 15.5 x 10.3

TSSOP (PW)

24

49.92 mm² 7.8 x 6.4

TVSOP (DGV)

24

32 mm² 5 x 6.4

2-V to 5.5-V V_CC Operation
Max t_pd of 15 ns at 5 V
Schmitt-Trigger Inputs Allow for Slow Input Rise/Fall Time
Polarity Control for Y Outputs Selects True or Complementary Logic
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>>2.3 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Partial-Power-Down Mode Operation
Supports Mixed-Mode Voltage Operation on All Ports
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

2-V to 5.5-V V_CC Operation
Max t_pd of 15 ns at 5 V
Schmitt-Trigger Inputs Allow for Slow Input Rise/Fall Time
Polarity Control for Y Outputs Selects True or Complementary Logic
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>>2.3 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Partial-Power-Down Mode Operation
Supports Mixed-Mode Voltage Operation on All Ports
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

The SN74LV8151 is a 10-bit universal Schmitt-trigger buffer with 3-state outputs, designed for 2-V to 5.5-V V_CC operation. The logic control (T/C\) pin allows the user to configure Y1 to Y8 as noninverting or inverting outputs. When T/C\ is high, the Y outputs are noninverted (true logic ), and when T/C\ is low, the Y outputs are inverted (complementary logic).

When output-enable (OE)\ input is low, the device passes data from Dn to Yn. When OE\ is high, the Y outputs are in the high-impedance state. The path A to P is a simple Schmitt-trigger buffer, and the path B to N is a simple Schmitt-trigger inverter.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74LV8151 is a 10-bit universal Schmitt-trigger buffer with 3-state outputs, designed for 2-V to 5.5-V V_CC operation. The logic control (T/C\) pin allows the user to configure Y1 to Y8 as noninverting or inverting outputs. When T/C\ is high, the Y outputs are noninverted (true logic ), and when T/C\ is low, the Y outputs are inverted (complementary logic).

When output-enable (OE)\ input is low, the device passes data from Dn to Yn. When OE\ is high, the Y outputs are in the high-impedance state. The path A to P is a simple Schmitt-trigger buffer, and the path B to N is a simple Schmitt-trigger inverter.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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