인터페이스 LVDS, M-LVDS 및 PECL

SN75LVDT1422

마지막 구매

전이중 시리얼라이저 및 디시리얼라이저

제품 상세 정보

Function SerDes Protocols Channel-Link I Supply voltage (V) 3.3 Signaling rate (MBits) 1400 Input signal LVDS Output signal LVDS, LVTTL Rating Catalog Operating temperature range (°C) -10 to 70
Function SerDes Protocols Channel-Link I Supply voltage (V) 3.3 Signaling rate (MBits) 1400 Input signal LVDS Output signal LVDS, LVTTL Rating Catalog Operating temperature range (°C) -10 to 70
TQFP (PAG) 64 144 mm² 12 x 12
  • 10 MHz to 100 MHz Shift Clock Support
  • 175 Mbytes/sec In TX/RX Modes
  • Reduces Cable Size, Cost, and System EMI
  • Bidirectional Data Communication
  • Total Power < 360 mW Typ at 100-MHz Worst Case Pattern
  • Power-Down Mode: < 500 µW Typ
  • No External Components Required for PLL
  • Inputs and Outputs Compatible with TIA/EIA-644 LVDS Standard
  • ESD Rating > 5 kV (HBM)
  • Integrated Termination Resistor
  • Supports Spread Spectrum Clocking
  • 64-Pin TQFP Package (PAG)
  • APPLICATIONS
    • Flash Memory Cards
    • Plain Paper Copiers
    • Printers

  • 10 MHz to 100 MHz Shift Clock Support
  • 175 Mbytes/sec In TX/RX Modes
  • Reduces Cable Size, Cost, and System EMI
  • Bidirectional Data Communication
  • Total Power < 360 mW Typ at 100-MHz Worst Case Pattern
  • Power-Down Mode: < 500 µW Typ
  • No External Components Required for PLL
  • Inputs and Outputs Compatible with TIA/EIA-644 LVDS Standard
  • ESD Rating > 5 kV (HBM)
  • Integrated Termination Resistor
  • Supports Spread Spectrum Clocking
  • 64-Pin TQFP Package (PAG)
  • APPLICATIONS
    • Flash Memory Cards
    • Plain Paper Copiers
    • Printers

The SN75LVDT1422 Full Duplex Serializer/Deserializer incorporates a 14-bit serializer and a 14-bit deserializer. Operation of the serializer is independent of the operation of the deserializer. The 14-bit serializer accepts 14 TTL input lines and generates 2 LVDS high-speed serial streams plus one LVDS clock signal. The 14-bit deserializer accepts 3 LVDS input signals (2 high-speed serial streams and one LVDS clock signal) and drives out 14 TTL data signals plus one TTL clock.

The serializer loads 14 data bits into registers upon the rising or falling edge of the input clock signal (CLK IN). Rising or falling edge operation can be selected via the R/F select pin for the transmitter only. The frequency of CLK IN is multiplied seven times and then used to unload the data registers in 7-bit slices. The two high-speed serial streams and a phase-locked clock (TCLK±) are then output to LVDS output drivers. The frequency of TCLK± is the same as the input clock, CLK IN.

The deserializer accepts data on two high-speed LVDS data lines. High-speed data is received and loaded into registers at the rate seven times the LVDS input clock (RCLK±). The data is then unloaded to a 14-bit wide LVTTL parallel bus at the RCLK± rate. The SN75LVDT1422 presents valid data on the falling edge of the output clock (CLK OUT).

The SN75LVDT1422 provides three termination resistors for the differential LVDS inputs thus minimizing cost, and board space, while providing better overall signal integrity (SI). The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user interventions are as follows:

Possible use of the TX ENABLE and RX ENABLE feature. Both the TX and RX ENABLE circuits are active-high inputs that independently enable the serializer and deserializer. When TX is disabled, the LVDS outputs go to high impedance. When RX is disabled, the TTL outputs go to a known low state.

The SN75LVDT1422 is characterized for operation over the free-air temperature range of -10°C to 70°C.

The SN75LVDT1422 Full Duplex Serializer/Deserializer incorporates a 14-bit serializer and a 14-bit deserializer. Operation of the serializer is independent of the operation of the deserializer. The 14-bit serializer accepts 14 TTL input lines and generates 2 LVDS high-speed serial streams plus one LVDS clock signal. The 14-bit deserializer accepts 3 LVDS input signals (2 high-speed serial streams and one LVDS clock signal) and drives out 14 TTL data signals plus one TTL clock.

The serializer loads 14 data bits into registers upon the rising or falling edge of the input clock signal (CLK IN). Rising or falling edge operation can be selected via the R/F select pin for the transmitter only. The frequency of CLK IN is multiplied seven times and then used to unload the data registers in 7-bit slices. The two high-speed serial streams and a phase-locked clock (TCLK±) are then output to LVDS output drivers. The frequency of TCLK± is the same as the input clock, CLK IN.

The deserializer accepts data on two high-speed LVDS data lines. High-speed data is received and loaded into registers at the rate seven times the LVDS input clock (RCLK±). The data is then unloaded to a 14-bit wide LVTTL parallel bus at the RCLK± rate. The SN75LVDT1422 presents valid data on the falling edge of the output clock (CLK OUT).

The SN75LVDT1422 provides three termination resistors for the differential LVDS inputs thus minimizing cost, and board space, while providing better overall signal integrity (SI). The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user interventions are as follows:

Possible use of the TX ENABLE and RX ENABLE feature. Both the TX and RX ENABLE circuits are active-high inputs that independently enable the serializer and deserializer. When TX is disabled, the LVDS outputs go to high impedance. When RX is disabled, the TTL outputs go to a known low state.

The SN75LVDT1422 is characterized for operation over the free-air temperature range of -10°C to 70°C.

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기술 문서

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모두 보기2
유형 직함 날짜
* Data sheet 14-Bit Full Duplex Serializer/Deserializer datasheet 2005/06/14
User guide ADS5500/5541/5542/5520/5521/5522 14-&12-Bit Single Channel ADC w/LVDT1422 Output 2006/07/26

설계 및 개발

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시뮬레이션 모델

SN75LVDT1422 IBIS Model

SLLC261.ZIP (21 KB) - IBIS Model
시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
시뮬레이션 툴

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사용 설명서: PDF
패키지 다운로드
TQFP (PAG) 64 옵션 보기

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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