ADC34RF72

現行

四通道、16 位元、1.5GSPS 超低雜訊頻譜密度 (NSD) 射頻取樣接收器

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產品規格表

document-pdfAcrobat ADC34RF72 Quad Channel 16-bit 1.5GSPS RF Sampling Data Converter datasheet (Rev. A) (英文) PDF | HTML

ADC34RF72

現行

產品規格表

立即訂購

產品詳細資料

Sample rate (max) (Msps)

1500

Resolution (Bits)

16

Number of input channels

4

Interface type

JESD204B, JESD204C

Analog input BW (MHz)

1800

Features

Bypass Mode, Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Internal Reference, Low power

Rating

Catalog

Peak-to-peak input voltage range (V)

1.4

Power consumption (typ) (mW)

4400

SNR (dB)

72.1

ENOB (Bits)

11.8

SFDR (dB)

68

Operating temperature range (°C)

-40 to 105

Input buffer

Yes

Sample rate (max) (Msps)

1500

Resolution (Bits)

16

Number of input channels

4

Interface type

JESD204B, JESD204C

Analog input BW (MHz)

1800

Features

Bypass Mode, Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Internal Reference, Low power

Rating

Catalog

Peak-to-peak input voltage range (V)

1.4

Power consumption (typ) (mW)

4400

SNR (dB)

72.1

ENOB (Bits)

11.8

SFDR (dB)

68

Operating temperature range (°C)

-40 to 105

Input buffer

Yes

FCCSP (ANH)

289

190.44 mm² (13.8 mm × 13.8 mm)

16-bit, quad channel 1.5GSPS ADC
Noise spectral density: -163.7dBFS/Hz
Thermal Noise: 75.6dBFS
Noise figure: 14.4dB
Single core (non-interleaved) ADC architecture
Aperture jitter: 40fs
Buffered analog inputs
Input fullscale: 1.44Vpp (4.1dBm)
Full power input bandwidth (-3dB): 1.8GHz
Ultra-low close-in residual phase noise:
- −140dBc/Hz at 10kHz offset at 1GHz
Spectral performance (fIN = 1GHz, -1dBFS):
- SNRflat: 72.1dBFS
- HD2,3: 68dBc
- Non HD2,3: 93dBFS
96-tap/ch programmable FIR equalizer filter
12-bit Fractional delay filter
Digital down-converters (DDCs)
- Up to 8 DDC
- Complex output: /2, /3, /4, /5 to /32768 decimation
- 48-bit NCO phase coherent frequency hopping
- Fast frequency hopping: < 1µs
JESD204B/C serial data interface
- Maximum lane rate: 24.75Gbps
Code error rate (CER): 1E-15 errors/sample
Power consumption: 1.1W/channel (1.5GSPS)

16-bit, quad channel 1.5GSPS ADC
Noise spectral density: -163.7dBFS/Hz
Thermal Noise: 75.6dBFS
Noise figure: 14.4dB
Single core (non-interleaved) ADC architecture
Aperture jitter: 40fs
Buffered analog inputs
Input fullscale: 1.44Vpp (4.1dBm)
Full power input bandwidth (-3dB): 1.8GHz
Ultra-low close-in residual phase noise:
- −140dBc/Hz at 10kHz offset at 1GHz
Spectral performance (fIN = 1GHz, -1dBFS):
- SNRflat: 72.1dBFS
- HD2,3: 68dBc
- Non HD2,3: 93dBFS
96-tap/ch programmable FIR equalizer filter
12-bit Fractional delay filter
Digital down-converters (DDCs)
- Up to 8 DDC
- Complex output: /2, /3, /4, /5 to /32768 decimation
- 48-bit NCO phase coherent frequency hopping
- Fast frequency hopping: < 1µs
JESD204B/C serial data interface
- Maximum lane rate: 24.75Gbps
Code error rate (CER): 1E-15 errors/sample
Power consumption: 1.1W/channel (1.5GSPS)

The ADC34RF72 is a 16-bit, 1.5GSPS (non-interleaved), quad channel analog to digital converter (ADC). The device is designed for the highest signal-to-noise ratio (SNR) and delivers a noise spectral density of −163.7dBFS/Hz. Using internal averaging modes, the NSD can be improved to as low as -168.7dBFS/Hz. The buffered analog inputs support a programmable internal termination impedance of 50, 100, 200Ω with a full power input bandwidth of 1.8GHz (−3dB).

The device includes several digital processing features such as a 96-tap/ch programmable FIR filter for equalization, a 12-bit fractional delay filter as well as multiple digital down converters (DDCs). There are eight DDCs supporting decimation factors of /2, /3 and /5 up to /32768. The 48-bit NCOs support phase coherent frequency hopping.

The ADC34RF72 supports the JESD204B/C serial data interface with interface rates up to 24.75Gbps. The power efficient ADC architecture consumes 1.1W/ch at 1.5GSPS and provides power scaling with lower sampling rates.

The ADC34RF72 is a 16-bit, 1.5GSPS (non-interleaved), quad channel analog to digital converter (ADC). The device is designed for the highest signal-to-noise ratio (SNR) and delivers a noise spectral density of −163.7dBFS/Hz. Using internal averaging modes, the NSD can be improved to as low as -168.7dBFS/Hz. The buffered analog inputs support a programmable internal termination impedance of 50, 100, 200Ω with a full power input bandwidth of 1.8GHz (−3dB).

The device includes several digital processing features such as a 96-tap/ch programmable FIR filter for equalization, a 12-bit fractional delay filter as well as multiple digital down converters (DDCs). There are eight DDCs supporting decimation factors of /2, /3 and /5 up to /32768. The 48-bit NCOs support phase coherent frequency hopping.

The ADC34RF72 supports the JESD204B/C serial data interface with interface rates up to 24.75Gbps. The power efficient ADC architecture consumes 1.1W/ch at 1.5GSPS and provides power scaling with lower sampling rates.

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重要文件	類型	標題	格式選項	下載最新的英文版本		日期
*	資料表	ADC34RF72 Quad Channel 16-bit 1.5GSPS RF Sampling Data Converter datasheet (Rev. A)	PDF \| HTML			2025/10/1
	類比設計期刊	高速轉換器奈奎斯特(Nyquist)孔周圍取樣	PDF \| HTML	Download English Version	PDF \| HTML	2025/5/23
	應用說明	Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends	PDF \| HTML			2025/3/28
	應用說明	Evaluating High-Speed, RF ADC Converter Front-end Architectures	PDF \| HTML			2025/3/26

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ADC34RF72EVM — ADC3xRF72 評估模組

ADC3xRF72EVM 評估模組 (EVM) 專為評估 ADC34RF7x 系列高速類比轉數位轉換器 (ADC) 所設計。ADC3xRF72EVM 配備一個 ADC3xRF72。ADC3xRF72 是一款具有 JESD 介面的 16 位元雙通道 ADC，執行取樣率高達 1.5GSPS。ADC3xRF72EVM 可評估所有裝置速度等級和通道數量：

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