ADC34RF72
- 16-bit, quad channel 1.5GSPS ADC
- Noise spectral density: -163.7dBFS/Hz
- Thermal Noise: 75.6dBFS
- Noise figure: 14.4dB
- Single core (non-interleaved) ADC architecture
- Aperture jitter: 40fs
- Buffered analog inputs
- Input fullscale: 1.44Vpp (4.1dBm)
- Full power input bandwidth (-3dB): 1.8GHz
- Ultra-low close-in residual phase noise:
- −140dBc/Hz at 10kHz offset at 1GHz
- Spectral performance (fIN = 1GHz, -1dBFS):
- SNRflat: 72.1dBFS
- HD2,3: 68dBc
- Non HD2,3: 93dBFS
- 96-tap/ch programmable FIR equalizer filter
- 12-bit Fractional delay filter
- Digital down-converters (DDCs)
- Up to 8 DDC
- Complex output: /2, /3, /4, /5 to /32768 decimation
- 48-bit NCO phase coherent frequency hopping
- Fast frequency hopping: < 1µs
- JESD204B/C serial data interface
- Maximum lane rate: 24.75Gbps
- Code error rate (CER): 1E-15 errors/sample
- Power consumption: 1.1W/channel (1.5GSPS)
The ADC34RF72 is a 16-bit, 1.5GSPS (non-interleaved), quad channel analog to digital converter (ADC). The device is designed for the highest signal-to-noise ratio (SNR) and delivers a noise spectral density of −163.7dBFS/Hz. Using internal averaging modes, the NSD can be improved to as low as -168.7dBFS/Hz. The buffered analog inputs support a programmable internal termination impedance of 50, 100, 200Ω with a full power input bandwidth of 1.8GHz (−3dB).
The device includes several digital processing features such as a 96-tap/ch programmable FIR filter for equalization, a 12-bit fractional delay filter as well as multiple digital down converters (DDCs). There are eight DDCs supporting decimation factors of /2, /3 and /5 up to /32768. The 48-bit NCOs support phase coherent frequency hopping.
The ADC34RF72 supports the JESD204B/C serial data interface with interface rates up to 24.75Gbps. The power efficient ADC architecture consumes 1.1W/ch at 1.5GSPS and provides power scaling with lower sampling rates.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | ADC34RF72 Quad Channel 16-bit 1.5GSPS RF Sampling Data Converter datasheet (Rev. A) | PDF | HTML | 2025年 10月 1日 |
| Analog Design Journal | 高速轉換器奈奎斯特(Nyquist)孔周圍取樣 | PDF | HTML | 2025年 5月 23日 | |
| Application note | Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends | PDF | HTML | 2025年 3月 28日 | |
| Application note | Evaluating High-Speed, RF ADC Converter Front-end Architectures | PDF | HTML | 2025年 3月 26日 |
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ADC34RF72EVM — ADC3xRF72 評估模組
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