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運算放大器 (op amps)
高速運算放大器 (GBW ≥ 50 MHz)

BUF802

現行

寬頻、2.3-nV/√Hz、高輸入阻抗 JFET 緩衝器

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產品規格表

BUF802

現行
產品規格表 立即訂購

產品詳細資料

Architecture FET / CMOS Input, Open Loop/Buffer Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 9 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 13 GBW (typ) (MHz) 3100 BW at Acl (MHz) 3100 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 7000 Vn at flatband (typ) (nV√Hz) 2.3 Vn at 1 kHz (typ) (nV√Hz) 10 Iq per channel (typ) (mA) 34 Vos (offset voltage at 25°C) (max) (mV) 800 Rail-to-rail No Features Adjustable BW/IQ/IOUT, Integrated Clamps Rating Catalog Operating temperature range (°C) -40 to 85 Input bias current (max) (pA) 25 Offset drift (typ) (µV/°C) 700 Iout (typ) (mA) 15 2nd harmonic (dBc) -55 3rd harmonic (dBc) -59 Frequency of harmonic distortion measurement (MHz) 1000
Architecture FET / CMOS Input, Open Loop/Buffer Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 9 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 13 GBW (typ) (MHz) 3100 BW at Acl (MHz) 3100 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 7000 Vn at flatband (typ) (nV√Hz) 2.3 Vn at 1 kHz (typ) (nV√Hz) 10 Iq per channel (typ) (mA) 34 Vos (offset voltage at 25°C) (max) (mV) 800 Rail-to-rail No Features Adjustable BW/IQ/IOUT, Integrated Clamps Rating Catalog Operating temperature range (°C) -40 to 85 Input bias current (max) (pA) 25 Offset drift (typ) (µV/°C) 700 Iout (typ) (mA) 15 2nd harmonic (dBc) -55 3rd harmonic (dBc) -59 Frequency of harmonic distortion measurement (MHz) 1000
VQFN (RGT) 16 9 mm² (3 mm × 3 mm)
  • Large-signal bandwidth (1VPP): 3.1GHz
  • Slew rate: 7000V/µs
  • Input voltage noise: 2.3nV/√Hz
  • 1% settling time: 0.7ns
  • Input-impedance: 50GΩ || 2.4pF
  • Capable of driving 50Ω load
  • Adjustable quiescent current for power and performance trade-off
  • Integrated input and output clamp with fast overdrive recovery
  • Voltage supply: ±4.5V to ±6.5V
  • Low phase noise
  • Large-signal bandwidth (1VPP): 3.1GHz
  • Slew rate: 7000V/µs
  • Input voltage noise: 2.3nV/√Hz
  • 1% settling time: 0.7ns
  • Input-impedance: 50GΩ || 2.4pF
  • Capable of driving 50Ω load
  • Adjustable quiescent current for power and performance trade-off
  • Integrated input and output clamp with fast overdrive recovery
  • Voltage supply: ±4.5V to ±6.5V
  • Low phase noise

The BUF802 device is an open-loop, unity gain buffer with a JFET input stage that offers low-noise, high-impedance buffering for data acquisition system (DAQ) front ends. The BUF802 supports DC-to-3.1GHz of bandwidth, while offering excellent distortion and noise performance across the frequency range.

The BUF802 can be used in a composite loop with a precision amplifier in applications where higher precision performance is required. The BUF802 uses a remarkable architecture to simplify the design of high-precision, wide-bandwidth composite loops.

The BUF802 features an adjustable quiescent current pin that enables designers to trade bandwidth and distortion for a lower quiescent current. This feature makes the device an excellent choice across a wide-frequency range. The BUF802 has integrated input and output clamps to protect the device and the subsequent signal-chain from overdrive voltages.

The BUF802 device is an open-loop, unity gain buffer with a JFET input stage that offers low-noise, high-impedance buffering for data acquisition system (DAQ) front ends. The BUF802 supports DC-to-3.1GHz of bandwidth, while offering excellent distortion and noise performance across the frequency range.

The BUF802 can be used in a composite loop with a precision amplifier in applications where higher precision performance is required. The BUF802 uses a remarkable architecture to simplify the design of high-precision, wide-bandwidth composite loops.

The BUF802 features an adjustable quiescent current pin that enables designers to trade bandwidth and distortion for a lower quiescent current. This feature makes the device an excellent choice across a wide-frequency range. The BUF802 has integrated input and output clamps to protect the device and the subsequent signal-chain from overdrive voltages.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 BUF802 Wide-Bandwidth, 2.3nV/√Hz, High-Input Impedance Buffer datasheet (Rev. E) PDF | HTML 2026/3/10
設計指南 High-Impedance, 500MHz Bandwidth Oscilloscope Analog Front End Reference Design PDF | HTML 2026/7/29
Product overview Pairing High-Speed JFET Amplifiers With Hi-Z DAQ Systems PDF | HTML 2024/4/8
應用說明 Choosing an Amplifier for Wide Bandwidth, High-Impedance, Data Acquisition AFEs PDF | HTML 2023/3/2
Application brief How to Tune the S-Parameters of Your Analog Front-End Signal Chain PDF | HTML 2022/2/25
技術文章 Achieving high-DC precision and wide large signal bandwidth with Hi-Z buffers PDF | HTML 2022/1/18

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

BUF802RGTEVM — BUF802 評估模組，採用 RGT 封裝的高速、寬頻、2.3-nV/√Hz、輸入緩衝器

BUF802RGTEVM 旨在輕鬆展示緩衝器的功能性和多元用途。此 EVM 配備兩種獨立的電路配置：採用精密放大器的複合迴路，以及獨立 BUF802 電路。可搭配分離式或單電源使用，並具備類比輸入和輸出上的 SMA 連接器，以方便操作。配置經過最佳化以減少寄生耦合，並在頻率範圍內提供最佳訊號保真。
使用指南: PDF | HTML
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模擬型號

BUF802 PSpice model

SBOMC43.ZIP (187 KB) - PSpice 模型
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模擬型號

BUF802 TINA-TI Reference Circuit (Rev. D)

SBOMBQ8D (5895 KB) - TINA-TI Spice 模型
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參考設計

TIDA-01022 — 適用於 DSO、雷達和 5G 無線測試系統的靈活 3.2-GSPS 多通道 AFE 參考設計

此高速多通道資料擷取參考設計可實現最佳系統性能。系統設計師需考量如高速多通道時脈產生的時脈抖動和偏斜等重要設計參數，這會影響整體系統 SNR、SFDR、通道對通道偏斜和確定性延遲。此參考設計展示了使用 JESD204B 高速資料轉換器、高速放大器、高性能時脈和低雜訊電源解決方案的多通道 AFE 和時脈解決方案，以實現最佳系統性能
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
VQFN (RGT) 16 Ultra Librarian
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