CDCEL925
- Member of programmable clock
generator family
- CDCEx913: 1PLL, 3 Outputs
- CDCEx925: 2PLL, 5 Outputs
- CDCEx925: 3PLL, 7 Outputs
- CDCEx949: 4PLL, 9 Outputs
- In-system programmability and
EEPROM
- Serial programmable volatile register
- Nonvolatile EEPROM to store customer settings
- Flexible input clocking concept
- External crystal: 8MHz to 32MHz
- On-chip VCXO: pull range ±150ppm
- Single-ended LVCMOS up to 160MHz
- Free selectable output frequency up to 230MHz
- Low-noise PLL core
- PLL loop filter components integrated
- Low period jitter (typical 60ps)
- Separate output supply pins
- CDCE925: 3.3V and 2.5V
- CDCEL925: 1.8V
- Flexible clock driver
- Three user-definable control inputs [S0/S1/S2], for example, SSC selection, frequency switching, output enable, or power down
- Generates highly accurate clocks for video, audio, USB, IEEE1394, RFID, Bluetooth, WLAN, Ethernet™, and GPS
- Generates common clock frequencies used with TI DaVinci™, OMAP™, DSPs
- Programmable SSC modulation
- Enables 0PPM clock generation
- 1.8V device power supply
- Wide temperature range: –40°C to 85°C
- Packaged in TSSOP
- Development and programming kit for easy PLL design and programming TI (Pro-Clock™)
The CDCE925 and CDCEL925 are modular PLL-based low-cost, high-performance, programmable clock synthesizers, multipliers, and dividers. CDCE925 and CDCEL925 generate up to five output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230MHz, using up to two independent configurable PLLs.
The CDCEx925 has a separate output supply pin, VDDOUT, which is 1.8V for CDCEL925 and 2.5V to 3.3V for CDCE925.
The input accepts an external crystal or LVCMOS clock signal. In case of a crystal input, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20pF. Additionally, an on-chip VCXO is selectable which allows synchronization of the output frequency to an external control signal, that is, PWM signal.
The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, Bluetooth, Ethernet, GPS), or interface (USB, IEEE1394, memory stick) clocks from a 27MHz reference input frequency, for example.
All PLLs support SSC (spread-spectrum clocking). SSC can be center-spread or down-spread clocking, which is a common technique to reduce electromagnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop filter components are automatically adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL.
The device supports nonvolatile EEPROM programming for easy customization of the device in the application. It is preset to a factory default configuration and can be reprogrammed to a different application configuration before it goes onto the PCB or reprogrammed by in-system programming. All device settings are programmable through the SDA/SCL bus, a 2-wire serial interface.
Three, free programmable control inputs, S0, S1, and S2, can be used to select different frequencies, or change the SSC setting for lowering EMI, or other control features like outputs disable to low, outputs in high-impedance state, power down, PLL bypass, and so forth.
The CDCx925 operates in a 1.8V environment and in a temperature range of –40°C to 85°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | CDCE(L)925: Flexible Low Power LVCMOS Clock Generator With SSC Support for EMI Reduction datasheet (Rev. J) | PDF | HTML | 2025/6/24 | ||
| 應用說明 | VCXO Application Guideline for CDCE(L)9xx Family (Rev. A) | 2012/4/23 | ||||
| 使用指南 | CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual (Rev. A) | 2010/11/22 | ||||
| 使用指南 | CDCE(L)9xx Performance Evaluation Module (Rev. A) | 2010/7/7 | ||||
| 應用說明 | Troubleshooting I2C Bus Protocol | 2009/10/19 | ||||
| 應用說明 | Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 | 2009/9/23 | ||||
| 應用說明 | Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency | 2008/3/31 | ||||
| 應用說明 | Practical consideration on choosing a crystal for CDCE(L)9xx family | 2008/3/24 | ||||
| 應用說明 | Clocking Recommendations for DM6446 Digital Video EVM with Sngle PLL (Rev. A) | 2007/8/8 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
CDCE925PERF-EVM — CDCE925 性能評估模組
The CDCE925Perf-Evaluation Module allows the verification of the functionality and performance of CDCE925 and CDCEL925 with the options of crystal and 1.8 V LVCMOS inputs. The outputs can be connected to the Oscilloscope directly with SMA cables.
CDCEL925PERF-EVM — CDCEL925 性能評估模組
The CDCEl925PERF-Evaluation Module will help to verify the functionality and performance of CDCEL925 with the options of crystal and 1.8 V LVCMOS inputs. The outputs can be connected to the Oscilloscope directly with SMA cables. The below information/items can be included: The EVM use's guide: (...)
CDCEL9XXPROGEVM — CDCE(L)949 系列 EEPROM 程式設計基板
The clock generator CDCE(L)949 family has integrated EEPROM that allows the default frequency settings to be saved upon start up. CDCEL9XXPROGEVM is a programming board that allows a fast programming of prototyping samples or small production quantities. It applies to all 8 devices in the family: (...)
SCAC131 — Drivers for the CDCEL9xx programmer EVM
CLOCKPRO — ClockPro Software
TI's ClockPro software allows users to program/configure the following devices in a friendly GUI interface:
- CDCE949
- CDCE937
- CDCE925
- CDCE913
- CDCE906
- CDCE706
- CDCEL949
- CDCEL937
- CDCEL925
- CDCEL913
It is intended to be used with the evaluation modules of the above devices.
SCAC073 — TI-Pro-Clock Programming Software
CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
時鐘樹架構是一款時鐘樹合成工具，可根據您的系統需求產生時鐘樹解決方案，進而簡化您的設計流程。此工具可從廣泛的計時產品資料庫中汲取資料，產生系統級多晶片計時解決方案。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 16 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。