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CDCE906

現行

167-MHz、LVCMOS、可編程的 3-PLL 時脈合成器/倍頻器/分頻器

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產品規格表

CDCE906

現行
產品規格表 立即訂購

產品詳細資料

Number of outputs 6 Output type LVCMOS Output frequency (max) (MHz) 167 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type Differential, LVCMOS, XTAL Operating temperature range (°C) 0 to 70 Features I2C, Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Catalog
Number of outputs 6 Output type LVCMOS Output frequency (max) (MHz) 167 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type Differential, LVCMOS, XTAL Operating temperature range (°C) 0 to 70 Features I2C, Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Catalog
TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm)
  • High Performance 3:6 PLL based Clock Synthesizer / Multiplier / Divider
  • User Programmable PLL Frequencies
  • EEPROM Programming Without the Need to Apply High Programming Voltage
  • Easy In-Circuit Programming via SMBus Data Interface
  • Wide PLL Divider Ratio Allows 0-ppm Output Clock Error
  • Generates Precise Video (27 MHz or 54 MHz) and Audio System Clocks from Multiple Sampling Frequencies (fS = 16, 22.05, 24, 32, 44.1, 48, 96 kHz)
  • Clock Inputs Accept a Crystal or a Single-Ended LVCMOS or a Differential Input Signal
  • Accepts Crystal Frequencies from 8 MHz up to 54 MHz
  • Accepts LVCMOS or Differential Input Frequencies up to 167 MHz
  • Two Programmable Control Inputs [S0/S1, A0/A1] for User Defined Control Signals
  • Six LVCMOS Outputs with Output Frequencies up to 167 MHz
  • LVCMOS Outputs can be Programmed for Complementary Signals
  • Free Selectable Output Frequency via Programmable Output Switching Matrix [6x6] Including 7-Bit Post-Divider for Each Output
  • PLL Loop Filter Components Integrated
  • Low Period Jitter (Typ 60 ps)
  • Features Spread Spectrum Clocking (SSC) for Lowering System EMI
  • Programmable Center Spread SSC Modulation (±0.1%, ±0.25%, and ±0.4%) with a Mean Phase Equal to the Phase of the Non-Modulated Frequency
  • Programmable Down Spread SSC Modulation (1%, 1.5%, 2%, and 3%)
  • Programmable Output Slew-Rate Control (SRC) for Lowering System EMI
  • 3.3-V Device Power Supply
  • Commercial Temperature Range 0°C to 70°C
  • Development and Programming Kit for Easy PLL Design and Programming
    (TI Pro-Clock™)
  • Packaged in 20-Pin TSSOP

Pro-Clock is a trademark of Texas Instruments.
  • High Performance 3:6 PLL based Clock Synthesizer / Multiplier / Divider
  • User Programmable PLL Frequencies
  • EEPROM Programming Without the Need to Apply High Programming Voltage
  • Easy In-Circuit Programming via SMBus Data Interface
  • Wide PLL Divider Ratio Allows 0-ppm Output Clock Error
  • Generates Precise Video (27 MHz or 54 MHz) and Audio System Clocks from Multiple Sampling Frequencies (fS = 16, 22.05, 24, 32, 44.1, 48, 96 kHz)
  • Clock Inputs Accept a Crystal or a Single-Ended LVCMOS or a Differential Input Signal
  • Accepts Crystal Frequencies from 8 MHz up to 54 MHz
  • Accepts LVCMOS or Differential Input Frequencies up to 167 MHz
  • Two Programmable Control Inputs [S0/S1, A0/A1] for User Defined Control Signals
  • Six LVCMOS Outputs with Output Frequencies up to 167 MHz
  • LVCMOS Outputs can be Programmed for Complementary Signals
  • Free Selectable Output Frequency via Programmable Output Switching Matrix [6x6] Including 7-Bit Post-Divider for Each Output
  • PLL Loop Filter Components Integrated
  • Low Period Jitter (Typ 60 ps)
  • Features Spread Spectrum Clocking (SSC) for Lowering System EMI
  • Programmable Center Spread SSC Modulation (±0.1%, ±0.25%, and ±0.4%) with a Mean Phase Equal to the Phase of the Non-Modulated Frequency
  • Programmable Down Spread SSC Modulation (1%, 1.5%, 2%, and 3%)
  • Programmable Output Slew-Rate Control (SRC) for Lowering System EMI
  • 3.3-V Device Power Supply
  • Commercial Temperature Range 0°C to 70°C
  • Development and Programming Kit for Easy PLL Design and Programming
    (TI Pro-Clock™)
  • Packaged in 20-Pin TSSOP

Pro-Clock is a trademark of Texas Instruments.

The CDCE906 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its small physical outlines, the CDCE906 is flexible. It has the capability to produce an almost independent output frequency from a given input frequency.

The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller.

To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output.

The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (e.g., a 27 MHz).

The CDCE906 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and PLL3 are designed for frequencies up to 167 MHz and optimized for zero-ppm applications with wide divider factors.

PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a common technique to reduce electro-magnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.

Based on the PLL frequency and the divider settings, the internal loop filter components will be automatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.

The device supports non-volatile EEPROM programming for easy-customized application. It is preprogrammed with a factory default configuration (see Figure 13) and can be reprogrammed to a different application configuration before it goes onto the PCB or reprogrammed by in-system programming. A different device setting is programmed via the serial SMBus interface.

Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).

The CDCE906 has three power supply pins, VCC, VCCOUT1 and VCCOUT2. VCC is the power supply for the device. It operates from a single 3.3-V supply voltage. VCCOUT1 and VCCOUT2 are the power supply pins for the outputs. VCCOUT1 supplies the outputs Y0 and Y1 and VCCOUT2 supplies the outputs Y2, Y3, Y4, and Y5. Both outputs supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output drive current is limited.

The CDCE906 is characterized for operation from 0°C to 70°C.

The CDCE906 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its small physical outlines, the CDCE906 is flexible. It has the capability to produce an almost independent output frequency from a given input frequency.

The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller.

To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output.

The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (e.g., a 27 MHz).

The CDCE906 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and PLL3 are designed for frequencies up to 167 MHz and optimized for zero-ppm applications with wide divider factors.

PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a common technique to reduce electro-magnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.

Based on the PLL frequency and the divider settings, the internal loop filter components will be automatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.

The device supports non-volatile EEPROM programming for easy-customized application. It is preprogrammed with a factory default configuration (see Figure 13) and can be reprogrammed to a different application configuration before it goes onto the PCB or reprogrammed by in-system programming. A different device setting is programmed via the serial SMBus interface.

Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).

The CDCE906 has three power supply pins, VCC, VCCOUT1 and VCCOUT2. VCC is the power supply for the device. It operates from a single 3.3-V supply voltage. VCCOUT1 and VCCOUT2 are the power supply pins for the outputs. VCCOUT1 supplies the outputs Y0 and Y1 and VCCOUT2 supplies the outputs Y2, Y3, Y4, and Y5. Both outputs supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output drive current is limited.

The CDCE906 is characterized for operation from 0°C to 70°C.
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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 Programmable 3-PLL Clock Synthesizer / Multiplier/Divider datasheet (Rev. H) 2007/12/11
應用說明 High Speed Layout Guidelines (Rev. A) 2017/8/8
使用指南 CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual (Rev. A) 2010/11/22
應用說明 Troubleshooting I2C Bus Protocol 2009/10/19
應用說明 CDCx706/x906 Termination and Signal Integrity Guidelines (Rev. A) 2007/11/28
使用指南 CDCE906/CDCE706 Performance EVM (Rev. B) 2007/4/17
應用說明 Clock Recommendations for the DM643x EVM 2006/11/29
應用說明 Recommended Terminations for the Differential Inputs of CDCE906/CDCE706 2006/8/10

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

CDCE906-706PERFEVM — CDCE906 & CDCE706 評估模組

CDCE906-706PERF-評估模組提供晶體差動與 LVCMOS 的輸入選項，可驗證 CDCE906 和 CDCE706 的功能與性能。六項輸出可以透過 SMA 纜線直接連接到示波器。
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開發板

CDCE906-706PROGEVM — CDCE906 和 CDCE706 可編程 EVM

使用指南: PDF
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應用軟體及架構

SCAC097 — Executable File Without LabVIEW 8.2 Run Time Engine

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支援軟體

CLOCKPRO — ClockPro Software

TI's ClockPro software allows users to program/configure the following devices in a friendly GUI interface:

  • CDCE949
  • CDCE937
  • CDCE925
  • CDCE913
  • CDCE906
  • CDCE706
  • CDCEL949
  • CDCEL937
  • CDCEL925
  • CDCEL913

It is intended to be used with the evaluation modules of the above devices.

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支援軟體

SCAC073 — TI-Pro-Clock Programming Software

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模擬型號

CDCE906 IBIS Model (Rev. A)

SCAC071 (646 KB) - IBIS 模型
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參考設計

TIDA-00080 — 基於隔離式 Delta-Sigma 調變器的 AC/DC 電壓和電流量測模組參考設計

這款隔離分流架構的電流量測單元無需使用電流變壓器 (CT) ，即可進行高準確度的電流量測。隔離是透過使用整合高電壓隔離與 ΔΣ 調變器的 AMC1304 來實現。此解決方案可消除客戶重視的 CT 需求，因為電路板尺寸會縮小、產品重量降低、系統串音與 EMI 減少，並以分流器取代 CT 來降低機械問題，進而延長產品使用壽命。

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參考設計

TIDA-00171 — 適用於馬達驅動器的隔離電流分流及電壓測量參考設計

此評估套件與參考設計在 C2000™ TMS320F28377D Delfino™ 微控制器中實作 AMC130x 強化型隔離 ΔΣ 調變器與整合式 Sinc 濾波器。此設計可評估這些量測的性能：三個馬達電流、三個逆變器電壓和 DC 鏈路電壓。  套件中提供的韌體，可用於配置 Sinc 濾波器、設定 PLL 頻率，以及從 Sinc 濾波器接收資料。另外也提供多用途執行階段 GUI，以協助使用者驗證 AMC130x 性能，並支援對 Delfino 控制器中的 Sinc 濾波器參數進行配置變更。

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封裝 針腳 CAD 符號、佔位空間與 3D 模型
TSSOP (PW) 20 Ultra Librarian
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