首頁 微控制器 (MCU) 與處理器 微處理器和 DSP 汽車駕駛輔助 SoC
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微控制器 (MCU) 與處理器
微處理器和 DSP
汽車駕駛輔助 SoC

TDA4AP-Q1

現行

具有八核 Arm® Cortex®-A72、24 TOPS AI 和 C7xDSP 的 SoC，用於視覺感知與分析

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產品規格表
使用指南

TDA4AP-Q1

現行
產品規格表 立即訂購

產品詳細資料

CPU 8 Arm Cortex-A72 Frequency (MHz) 2000 Coprocessors 8 Arm Cortex-R5F Display type 1 EDP, 2 DSI, MIPI DPI Protocols Ethernet PCIe 2 PCIe Gen 3 Hardware accelerators C7™ NPU, Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator Features Vision Analytics Operating system AutoSAR, FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage Rating Automotive Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled Edge AI Studio enabled, NPU accelerated, Yes
CPU 8 Arm Cortex-A72 Frequency (MHz) 2000 Coprocessors 8 Arm Cortex-R5F Display type 1 EDP, 2 DSI, MIPI DPI Protocols Ethernet PCIe 2 PCIe Gen 3 Hardware accelerators C7™ NPU, Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator Features Vision Analytics Operating system AutoSAR, FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage Rating Automotive Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled Edge AI Studio enabled, NPU accelerated, Yes
FCBGA (ALY) 1414 961 mm² (31 mm × 31 mm)

Processor cores:

  • Up to Four C7x floating point, vector DSP, up to 1.0GHz, 320GFLOPS, 1024GOPS
  • Up to Four Deep-learning matrix multiply accelerator (MMAv2), up to 32TOPS (8b) at 1.0GHz
  • Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Eight Arm Cortex-A72 microprocessor subsystem at up to 2.0GHz
    • 2MB shared L2 cache per quad-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Eight Arm Cortex-R5F MCUs at up to 1.0GHz
    • 32K I-Cache, 32K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Six Arm Cortex-R5F MCUs in general compute partition
  • GPU IMG BXS-4-64, 256kB Cache, up to 800MHz, 50GFLOPS, 4GTexels/s
  • Custom-designed interconnect fabric supporting near max processing entitlement

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Four External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266MT/s
    • Up to 4x32-b bus with inline ECC up to 68GB/s
  • General-Purpose Memory Controller (GPMC)
  • 3x512KB on-chip SRAM in MAIN domain, protected by ECC

    Functional Safety:

  • Functional Safety-Compliant (on select part numbers)
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262/IEC 61508 functional safety system design up to ASIL D/SIL 3
    • Systematic capability up to ASIL D/SC 3
    • Hardware integrity up to ASIL D/SIL 3 for MCU Domain
    • Hardware integrity up to ASIL B/SIL 2 for Main Domain
    • Hardware integrity up to ASIL D/SIL 3 for Extended MCU (EMCU) portion of the Main Domain
  • Safety-related certification
  • AEC-Q100 qualified on part number variants ending in Q1

    Device security (on select part numbers):

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated Ethernet switch supporting up to 8 (TDA4xH) or 4 (TDA4xP) external ports
    • Two ports support 5Gb, 10Gb USXGMII/XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 2 (TDA4xH) or 1 (TDA4xP) QSGMII can be enabled and uses all 8 or 4 internal lanes
  • Up to 4x2-L/2x4L (TDA4xH) or 2x2L/1x4L (TDA4xP) PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Three CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
    • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
    • CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
    • CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane
    • ECC verification/correction with CRC check + ECC on RAM
    • Virtual Channel support (up to 16)
    • Ability to write stream data directly to DDR via DMA

    Ethernet:

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Display subsystem:

  • Two DSI 4L TX (up to 2.5k)
  • One eDP/DP interface with Multi-Display Support (MST)
  • One DPI

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Video acceleration:

  • H.264/H.265 Encode/Decode, up to 960MP/s (TDA4xH) or 480MP/s (TDA4xP)

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 31mm × 31mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety-Compliant support up to ASIL D/SIL 3
  • Flexible mapping to support different use cases

Processor cores:

  • Up to Four C7x floating point, vector DSP, up to 1.0GHz, 320GFLOPS, 1024GOPS
  • Up to Four Deep-learning matrix multiply accelerator (MMAv2), up to 32TOPS (8b) at 1.0GHz
  • Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Eight Arm Cortex-A72 microprocessor subsystem at up to 2.0GHz
    • 2MB shared L2 cache per quad-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Eight Arm Cortex-R5F MCUs at up to 1.0GHz
    • 32K I-Cache, 32K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Six Arm Cortex-R5F MCUs in general compute partition
  • GPU IMG BXS-4-64, 256kB Cache, up to 800MHz, 50GFLOPS, 4GTexels/s
  • Custom-designed interconnect fabric supporting near max processing entitlement

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Four External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266MT/s
    • Up to 4x32-b bus with inline ECC up to 68GB/s
  • General-Purpose Memory Controller (GPMC)
  • 3x512KB on-chip SRAM in MAIN domain, protected by ECC

    Functional Safety:

  • Functional Safety-Compliant (on select part numbers)
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262/IEC 61508 functional safety system design up to ASIL D/SIL 3
    • Systematic capability up to ASIL D/SC 3
    • Hardware integrity up to ASIL D/SIL 3 for MCU Domain
    • Hardware integrity up to ASIL B/SIL 2 for Main Domain
    • Hardware integrity up to ASIL D/SIL 3 for Extended MCU (EMCU) portion of the Main Domain
  • Safety-related certification
  • AEC-Q100 qualified on part number variants ending in Q1

    Device security (on select part numbers):

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated Ethernet switch supporting up to 8 (TDA4xH) or 4 (TDA4xP) external ports
    • Two ports support 5Gb, 10Gb USXGMII/XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 2 (TDA4xH) or 1 (TDA4xP) QSGMII can be enabled and uses all 8 or 4 internal lanes
  • Up to 4x2-L/2x4L (TDA4xH) or 2x2L/1x4L (TDA4xP) PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Three CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
    • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
    • CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
    • CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane
    • ECC verification/correction with CRC check + ECC on RAM
    • Virtual Channel support (up to 16)
    • Ability to write stream data directly to DDR via DMA

    Ethernet:

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Display subsystem:

  • Two DSI 4L TX (up to 2.5k)
  • One eDP/DP interface with Multi-Display Support (MST)
  • One DPI

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Video acceleration:

  • H.264/H.265 Encode/Decode, up to 960MP/s (TDA4xH) or 480MP/s (TDA4xP)

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 31mm × 31mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety-Compliant support up to ASIL D/SIL 3
  • Flexible mapping to support different use cases

The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in an functional safety compliant targeted architecture make the TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 devices a great fit for several imaging, vision, radar, sensor fusion and AI applications such as: Robotics, Mobile machineries, Off-highway vehicle controller, Machine Vision, AI BOX, Gateways, Retail automation, Medical Imaging, and so on. The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview

The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. A single instance of the new “MMAv2” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.

General Compute Cores and Integration Overview

Separate eight core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Eight Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72’s unencumbered for applications. The integrated IMG BXS-4-64 GPU offers up to 50 GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 family also includes an MCU island eliminating the need for an external system microcontroller.

The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in an functional safety compliant targeted architecture make the TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 devices a great fit for several imaging, vision, radar, sensor fusion and AI applications such as: Robotics, Mobile machineries, Off-highway vehicle controller, Machine Vision, AI BOX, Gateways, Retail automation, Medical Imaging, and so on. The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview

The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. A single instance of the new “MMAv2” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.

General Compute Cores and Integration Overview

Separate eight core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Eight Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72’s unencumbered for applications. The integrated IMG BXS-4-64 GPU offers up to 50 GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 family also includes an MCU island eliminating the need for an external system microcontroller.
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TDA4VH-Q1 現行 具備八核心 Arm® Cortex®-A72、32 TOPS AI 效能、C7xDSP 與 GPU 的 SoC，用於視覺感知與分析 Eight Cortex-A72 cores (100K DMIPS), 32 TOPS AI performance, four LPDDR4 interfaces; includes GPU, video encode and decode and eight port Ethernet switch
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TDA4AH-Q1 現行 具有八核 Arm® Cortex®-A72、C7xDSP 與 32 TOPS AI 的 SoC，用於視覺感知與分析 Analytics-focused SoC; eight Cortex-A72 (100K DMIPS), 32 TOPS AI performance; does not inlcude GPU, video encode only
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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 TDA4VH-Q1, TDA4AH-Q1, TDA4VP-Q1, TDA4AP-Q1 Jacinto™ Processors datasheet (Rev. C) PDF | HTML 2025/11/4
* 使用指南 J784S4 J742S2 Technical Reference Manual (Rev. E) PDF | HTML 2025/9/9
* 勘誤表 J784S4, TDA4AP, TDA4VP, TDA4AH, TDA4VH, AM69A Processors Silicon Revision 1.0 (Rev. C) PDF | HTML 2026/6/12
EVM User's guide AM69 Processor Starter Kit Evaluation Module (Rev. B) PDF | HTML 2026/6/29
Application brief SPL Boot Time Optimizations on Jacinto SoCs PDF | HTML 2026/6/9
Product overview TIDLRunner: Simplifying the 'Bring Your Own Model' Development Flow for Edge AI Accelerated Processors PDF | HTML 2026/5/14
白皮書 Securing the Future: Cyber Resilience Act (EU-CRA) Compliance with TI’s Jacinto and Sitara Processors PDF | HTML 2026/4/24
應用說明 Tuning QoS and CoS Settings for DDR Bandwidth Optimization on TDA4x and AM6x Devices (Rev. A) PDF | HTML 2026/3/23
功能安全資訊 Confirmation of Software Component Qualification for JACINTO IPC for J721E, J721S2, J7200, J784S4, and J742S2 PDF | HTML 2026/3/19
應用說明 Boot Flow Options on TDA4 Devices PDF | HTML 2026/1/5
功能安全資訊 J721E, J721S2, J7200, J784S4, and J742S2 TÜV SÜD Letter of Confirmation for Software Component Qualification 2025/10/1
功能安全資訊 J7200, J721E, J721S2, J722S, J742S2, and J784S4 SDL TÜV SÜD Functional Safety Certificate (Rev. A) 2025/9/25
功能安全資訊 J721E, J721S2, J7200, J722S, J742S2, J784S4 MCAL TÜV SÜD Functional Safety Certificate (Rev. A) 2025/9/25
功能安全資訊 TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. D) 2025/6/17
功能安全資訊 J784S4: TDA4VH TDA4AH TDA4VP TDA4AP SN17 SN18, J742S2: TDA4VPE TDA4APE SN16 TÜV Functional Safety Certificate 2025/6/11
使用指南 Powering Jacinto 7 SoC For Isolated Power Groups With TPS6594133A-Q1 + Dual HCPS (Rev. A) PDF | HTML 2025/5/16
應用說明 MCAN Debug Guide PDF | HTML 2025/2/18
應用說明 Microcontroller Abstraction Layer on Jacinto™ and Sitara™ Embedded Processors PDF | HTML 2025/1/28
使用指南 J784S4, TDA4VH, TDA4AH, TDA4VP, TDA4AP, AM69 Power Estimation Tool User’s Guide (Rev. A) PDF | HTML 2024/12/23
應用說明 Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F) PDF | HTML 2024/8/5
應用說明 Debugging GPU Driver Issues on TDA4x and AM6x Devices PDF | HTML 2024/6/20
應用說明 Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines (Rev. A) PDF | HTML 2024/6/4
應用說明 MMC SW Tuning Algorithm (Rev. A) PDF | HTML 2024/5/14
應用說明 Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist (Rev. B) PDF | HTML 2024/4/4
技術文章 Building multicamera vision perception systems for ADAS domain controllers with integrated processors PDF | HTML 2024/1/5
技術文章 How to deliver current beyond 100 A to an ADAS processor PDF | HTML 2024/1/4
應用說明 Jacinto7 HS Device Customer Return Process PDF | HTML 2023/11/16
白皮書 以高度整合處理器設計高效邊緣 AI 系統 (Rev. A) PDF | HTML Download English Version (Rev.A) PDF | HTML 2023/4/19
應用說明 UART Log Debug System on Jacinto 7 SoC PDF | HTML 2023/1/9
Product overview Jacinto™ 7 Safety Product Overview PDF | HTML 2022/8/15
應用說明 Dual-TDA4x System Solution PDF | HTML 2022/4/29
應用說明 SPI Enablement & Validation on TDA4 Family PDF | HTML 2022/4/5
技術文章 How are sensors and processors creating more intelligent and autonomous robots? PDF | HTML 2022/3/29
技術文章 How to simplify your embedded edge AI application development PDF | HTML 2022/1/28
應用說明 Enabling MAC2MAC Feature on Jacinto7 Soc 2022/1/10
功能安全資訊 Leverage Jacinto 7 Processors Functional Safety Features for Automotive Designs (Rev. A) PDF | HTML 2021/10/13
應用說明 TDA4 Flashing Techniques PDF | HTML 2021/7/8
白皮書 Security Enablers on Jacinto™ 7 Processors 2021/1/4
白皮書 Enabling Differentiation through MCU Integration on Jacinto™ 7 Processors 2020/10/22
應用說明 OSPI Tuning Procedure PDF | HTML 2020/7/8

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開發板

J784S4XEVM — TDA4AP、TDA4VP、TDA4AH 與 TDA4VH 評估模組

J784S4 評估模組 (EVM) 是評估 TDA4AP-Q1、TDA4VP-Q1、TDA4AH-Q1 和 TDA4VH-Q1 處理器在汽車與工業市場中之視覺分析與網路應用的平台。這些處理器在多攝影機、感測器融合與先進駕駛輔助系統 (ADAS) 網域控制應用中的表現尤佳。

TDA4AP-Q1、TDA4VP-Q1、TDA4AH-Q1 和 TDA4VH-Q1 處理器採用功能強大的異質架構，其中包括 DSP 核心組合、Arm® Cortex®-A72 核心、適用於人工智慧 (AI) 的矩陣數學加速、整合式影像訊號處理器 (ISP) 和視覺處理加速、3D 圖形處理單元 (GPU) (...)

使用指南: PDF | HTML
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開發板

J7EXPA01EVM — Fusion2 序列擷取擴充板套件

擴充 Jacinto7 EVM 的功能，以開發及評估可讓開發人員圍繞 Jacinto7 系列處理器開發硬體及寫入軟體的系統。可使用 Fusion2 擴充卡，將其他功能新增至 EVM/SK

Fusion2 序列擷取電路板能夠介接 Jacinto7 處理器與外部攝影機感測器、雷達感測器和其他類似擷取裝置。  支援最多十二個高速資料來源輸入，並結合為數位 MIPI CSI-2 訊號。 
 

使用指南: PDF | HTML
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開發板

J7EXPCXEVM — 閘道/乙太網路交換器擴充卡

Expand the capabilities of the J721EXCP01EVM common processor board for evaluating Jacinto 7 processors in vision analytics and networking applications in automotive and industrial markets with our Gateway/Ethernet switch expansion card.

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開發板

J7EXPEXEVM — 音訊和顯示擴充卡

Expand the capabilities of the J721EXCP01EVM common processor board for evaluating Jacinto 7 processors in vision analytics and networking applications in automotive and industrial markets with our audio and display expansion card.
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偵錯探測器

TMDSEMU110-U — XDS110 JTAG 偵錯探測器

德州儀器 XDS110 是一種全新的偵錯探測器 (模擬器) 類別，適用於 TI 嵌入式處理器。XDS110 取代 XDS100 系列，可在單一 Pod 中支援更廣泛的標準 (IEEE1149.1、IEEE1149.7、SWD)。同時，所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。  對於針腳上的核心追蹤，則需要 XDS560v2 PRO TRACE。

德州儀器 XDS110 透過 TI 20 針腳連接器（具有用於 TI 14 針腳和 Arm 10 針腳和 Arm 20 針腳的多轉接器）連接到目標電路板，並透過 USB2.0 (...)

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偵錯探測器

TMDSEMU560V2STM-U — XDS560™ 軟體 v2 系統追蹤 USB 偵錯探測器

XDS560v2 是 XDS560™ 系列偵錯探測器中性能最高的，且同時支援傳統 JTAG 標準 (IEEE1149.1) 與 cJTAG (IEEE1149.7)。  請注意，其不支援序列線偵錯 (SWD)。

所有 XDS 偵錯探測器均在所有配備嵌入式追蹤緩衝器 (ETB) 的 ARM 與 DSP 處理器中支援核心與系統追蹤。  對於針腳上的追蹤，則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (...)

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偵錯探測器

LB-3P-TRACE32-ARM — 適用於 Arm® 架構微控制器和處理器的 Lauterbach TRACE32® 偵錯和追蹤系統

Lauterbach 的 TRACE32® 工具是一套先進的軟硬體元件，可讓開發人員分析、最佳化及認證各種 Arm® 架構微控制器和處理器。全球知名的嵌入式系統和 SoC 偵錯和追蹤解決方案是完美的解決方案，適用於從早期的矽前 (pre-silicon) 開發，到產品認證和現場故障排除等所有開發階段。Lauterbach 工具的直覺模組化設計為工程師提供現今最高的可用性能，以及可隨需求變化而調整和成長的系統。藉由 TRACE32® 偵錯器，開發人員也可透過單一偵錯介面，同時偵錯和控制 SoC 中的任何 C28x/C29x/C6x/C7x DSP 核心及所有其他 Arm (...)

從：Lauterbach GmbH
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偵錯探測器

TSK-3P-BLUEBOX — TASKING BlueBox hardware debugger

TASKING’s Debug, Trace, and Test tools offer comprehensive solutions for efficient debugging, tracing, and testing of TI's embedded systems. The scalable TASKING BlueBox debuggers allow users to easily flash, debug, and test across TI's portfolio. Development on TI hardware is made even easier with (...)

從：TASKING Germany GmbH
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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-J784S4 — Linux® SDK for TDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1

J784S4 處理器軟體開發套件 (SDK) 即時作業系統 (RTOS) 可搭配處理器 SDK Linux® 或處理器 SDK QNX®，在我們的 Jacinto™ 平台組成 TTDA4AP-Q1、TDA4VP-Q1、TDA4AH-Q1 和 TDA4VH-Q1 晶片系統 (SoC) 的多處理器軟體開發平台。

PROCESSOR-SDK-J784S4 提供完整軟體工具組和零組件，有助於使用者開發與部署在支援的 J784S4 SoC 上之應用。SDK RTOS 及處理器 SDK Linux 或處理器 SDK QNX 可搭配使用，共同實作各種機器人、視覺、工廠與建築自動化及汽車先進駕駛輔助系統 (...)

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軟體開發套件 (SDK)

PROCESSOR-SDK-QNX-J784S4 — QNX SDK for TDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1

J784S4 處理器軟體開發套件 (SDK) 即時作業系統 (RTOS) 可搭配處理器 SDK Linux® 或處理器 SDK QNX®，在我們的 Jacinto™ 平台組成 TTDA4AP-Q1、TDA4VP-Q1、TDA4AH-Q1 和 TDA4VH-Q1 晶片系統 (SoC) 的多處理器軟體開發平台。

PROCESSOR-SDK-J784S4 提供完整軟體工具組和零組件，有助於使用者開發與部署在支援的 J784S4 SoC 上之應用。SDK RTOS 及處理器 SDK Linux 或處理器 SDK QNX 可搭配使用，共同實作各種機器人、視覺、工廠與建築自動化及汽車先進駕駛輔助系統 (...)

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軟體開發套件 (SDK)

PROCESSOR-SDK-RTOS-J784S4 — RTOS SDK for TDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1

J784S4 處理器軟體開發套件 (SDK) 即時作業系統 (RTOS) 可搭配處理器 SDK Linux® 或處理器 SDK QNX®，在我們的 Jacinto™ 平台組成 TTDA4AP-Q1、TDA4VP-Q1、TDA4AH-Q1 和 TDA4VH-Q1 晶片系統 (SoC) 的多處理器軟體開發平台。

PROCESSOR-SDK-J784S4 提供完整軟體工具組和零組件，有助於使用者開發與部署在支援的 J784S4 SoC 上之應用。SDK RTOS 及處理器 SDK Linux 或處理器 SDK QNX 可搭配使用，共同實作各種機器人、視覺、工廠與建築自動化及汽車先進駕駛輔助系統 (...)

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軟體開發套件 (SDK)

IBV-3P-ICECAT — 適用於嵌入式系統的 IBV EtherCAT MainDevice SDK

The icECAT EtherCAT Master Stack library by IBV is a Software Development Kit (SDK) for creating an EtherCAT MainDevice (master) system achieving best performance with lowest resource usage. It is especially designed for use on embedded systems with optimized Link Layer drivers with DMA support (...)

從：IBV - Echtzeit- und Embedded GmbH & Co. KG
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IDE、配置、編譯器或偵錯程式

C7000-CGT — C7000 代碼產生工具 - 編譯器

The TI C7000 C/C++ compiler tools are an essential component of the CCStudio™ development ecosystem, providing robust support for TI C7000™ digital signal processor cores. They are engineered to maximize the potential of high-performance C7000-based platforms.

The CCStudio™ IDE is the integrated (...)

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CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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IDE、配置、編譯器或偵錯程式

DDR-CONFIG-J784S4 — DDR 配置工具

This SysConfig based tool simplifies the process of configuring the DDR Subsystem Controller and PHY to interface to SDRAM devices. Based on the memory device, board design, and topology the tool outputs files to initialize and train the selected memory.
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SAFETI_CQKIT — 安全編譯器資格套件

開發安全編譯器資格認證套件是為了協助客戶對 TI ARM、C6000、C7000 或 C2000/CLA C/C++ 編譯器的使用進行認證，以確保符合功能安全標準，如 IEC 61508 和 ISO 26262。

安全編譯器資格認證套件：

  • 對 TI 客戶免費
  • 不需要使用者進行資格測試
  • 支援編譯器覆蓋範圍分析*
    • * 覆蓋範圍資料收集的說明可從每個 QKIT 下載頁面下載。
  • 不包括 Validas 諮詢

如需存取安全編譯器資格認證套件，請按一下上面其中一個索取按鈕。

如需進一步了解功能安全產品，請造訪 (...)

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IDE、配置、編譯器或偵錯程式

SYSCONFIG — 系統配置工具

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

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TSK-3P-VX-TOOLSET — 適用於 Arm 的 TASKING VX 工具套件

適用於 Arm 的 VX 工具套件是一套經過認證的編譯器工具鏈，可用於指定 Cortex-M 與 Cortex-R 核心裝置的安全關鍵嵌入式軟體開發。透過整合 Eclipse IDE、進階多核心支援，以及與 TASKING BlueBox 除錯器的相容性，VX 工具套件可簡化開發流程。通過 TÜV NORD 認證，符合 ISO 26262（最高支援 ASIL D）及 ISO 21434 標準。

從：TASKING Germany GmbH
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作業系統 (OS)

GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
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作業系統 (OS)

GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS

The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)

從：Green Hills Software
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作業系統 (OS)

QNX-3P-NEUTRINO-RTOS — QNX Neutrino RTOS

QNX Neutrino® 即時作業系統 (RTOS) 是一款功能完整且穩固的 RTOS，專為實現適用於汽車、醫療、運輸、軍事和工業嵌入式系統的新一代產品而設計。微核心設計與模組化架構，能讓客戶以低整體擁有成本打造高度最佳化且可靠的系統。
從：QNX
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作業系統 (OS)

WHIS-3P-SAFERTOS — WITTENSTEIN SAFERTOS 預先認證的安全 RTOS

SAFERTOS® 是專為嵌入式處理器設計的獨特即時作業系統。經 TÜV SÜD 預先認證，符合 IEC 61508 SIL3 與 ISO 26262 ASILD 標準。SAFERTOS® 是由 WHIS 專家團隊專為安全而打造，適用於全球重要安全應用。WHIS 與德州儀器的合作已經超過十年。在此期間，WHIS 已將 SAFERTOS® 移植至各種 TI 處理器，支援所有熱門核心，並可依要求提供其他架構。SAFERTOS® 專為您的特定處理器/編譯器組合量身打造，隨附完整的原始程式碼與設計保證包，可完全一目了然整個設計生命週期。許多 WHIS 客戶開始使用 FreeRTOS (...)

從：WITTENSTEIN High Integrity Systems
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韌體

USIT-3P-SECIC-HSM — Uni-Sentry SecIC-HSM 韌體

SecIC-HSM 旨在滿足 MCU/SoC 晶片所需的網路安全要求。HSM 韌體可應用於汽車、新能源、光伏、機器人、醫療保健與航空等領域。提供的網路安全功能包括安全開機、安全通訊 (SecOC)、安全診斷、安全儲存、安全更新、安全偵錯和金鑰管理。SecIC-HSM 的優點：一站式網路安全解決方案，具備跨晶片系列的全方位軟體相容性，擁有業界領先的性能，已在近 30 家 OEM 的量產車型中成功部署，累計出貨超過 300 萬套。

從：Shanghai Uni-Sentry Intelligent Technology Co., LTD
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韌體

USIT-3P-SECIC-PQC — Uni-Sentry SecIC-PQC 演算法韌體

Uni-Sentry 的安全解決方案採用 PQC 演算法，能夠抵抗量子電腦對傳統加密演算法所造成的解密威脅。PQC 韌體與硬體安全模組 (HSM) 進行協同優化，利用硬體加速與安全性強化，以提升加密演算法的執行效率與安全性。 


Uni-Sentry 持續監控全球量子運算的發展，並更新其演算法組合。當前的 PQC 產品功能包括：

  • SP 800-208：LMS 和 XMSS
  • FIPS 203 (ML-KEM)：CRYSTALS-KYBER
  • FIPS 204 (ML-DSA)：CRYSTALS-Dilithium
  • FIPS 205 (SLH-DSA)： SPHINCS+ 

技術亮點 

  • 量子抗性認證：與 (...)
從：Shanghai Uni-Sentry Intelligent Technology Co., LTD
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模擬型號

AM69 TDA4VH TDA4AH TDA4VP TDA4AP Thermal Model (Rev. A)

SPRM843A.ZIP (0 KB) - 熱模型
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模擬型號

AM69A,TDA4VH-Q1,TDA4AH-Q1,TDA4VP-Q1,TDA4AP-Q1 BSDL MODEL

SPRM840.ZIP (18 KB) - BSDL 模型
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模擬型號

IBIS Model for AM69 TDA4VH TDA4AH TDA4VP TDA4AP

SPRM836.ZIP (1497 KB) - IBIS 模型
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCBGA (ALY) 1414 Ultra Librarian
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