Low cost, high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765, a low noise frequency synthesizer, generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and SFDR performance.
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Reference design overview and verified performance test data
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Detailed overview of design layout for component placement
Files used for 3D models or 2D drawings of IC components
Files used for 3D models or 2D drawings of IC components
PCB layer plot file used for generating PCB design layout
Includes TI products in the design and potential alternatives.
The ADC12J4000EVM is an evaluation module (EVM) that allows for the evaluation of TI's ADC12J4000. The ADC12J4000 is a low power, 12-bit, 4-GSPS RF-sampling analog to digital converter (ADC) with a buffered analog input, integrated Digital Down Converter with programmable NCO and decimation settings (...)
| Type | Title | Date | |
|---|---|---|---|
| * | Design guide | Clock Solution for GSPS ADCs Design Guide | Mar. 06, 2015 |
| User guide | TIDA-00359 Gerber | Mar. 06, 2015 |
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