Clocking Solution Reference Design for GSPS ADCs


Design files


Low cost, high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765, a low noise frequency synthesizer, generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and SFDR performance.

  • Frequency ranges from 300MHz to 4.8GHz
  • Low noise VCO ~ 133dBc/Hz
  • Low jitter: 0.35ps
  • This reference design is tested and includes an evaluation board, configuration software and User's Guide
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Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDU829.PDF (373 K)

Reference design overview and verified performance test data

TIDRD88.PDF (1278 K)

Detailed schematic diagram for design layout and components

TIDRD89.PDF (61 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRD90.PDF (1261 K)

Detailed overview of design layout for component placement

TIDRD92.ZIP (10461 K)

Files used for 3D models or 2D drawings of IC components

TIDRD93.ZIP (3547 K)

Files used for 3D models or 2D drawings of IC components

TIDRD91.PDF (6792 K)

PCB layer plot file used for generating PCB design layout


Includes TI products in the design and potential alternatives.

AC/DC & DC/DC converters (integrated FET)

TPS543274.5V to 18V Input, 3-A Synchronous Step-Down Converter

Data sheet: PDF | HTML
Clock jitter cleaners & synchronizers

LMK04828Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Data sheet: PDF | HTML
Direction-controlled voltage translators

SN74AVC4T774Four-bit dual-supply bus transceiver with configurable voltage-level shifting and tri-state outputs

Data sheet: PDF | HTML
High-speed ADCs (≥10 MSPS)

ADC12J400012-Bit, 4.0-GSPS, RF Sampling Analog-to-Digital Converter (ADC)

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

LP385133-A, ultra-low-dropout voltage regulator with power good & enable for 1.8 V

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS749013-A, low-VIN (0.8-V) adjustable ultra-low-dropout voltage regulator with power good and enable

Data sheet: PDF | HTML
RF PLLs & synthesizers

TRF3765300M-4800MHz Low Noise Integer-N/Fractional-N PLL with Integrated VCO and up to 8 Outputs

Data sheet: PDF | HTML

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Evaluation board

ADC12J4000EVM — ADC12J4000 12-Bit, 4.0-GSPS, RF Sampling Analog-to-Digital Converter Evaluation Module

The ADC12J4000EVM is an evaluation module (EVM) that allows for the evaluation of TI's ADC12J4000. The ADC12J4000 is a low power, 12-bit, 4-GSPS RF-sampling analog to digital converter (ADC) with a buffered analog input, integrated Digital Down Converter with programmable NCO and decimation (...)

User guide: PDF
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Technical documentation

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Type Title Date
* Design guide Clock Solution for GSPS ADCs Design Guide Mar. 06, 2015
User guide TIDA-00359 Gerber Mar. 06, 2015

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