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TIDA-00359

Clocking Solution Reference Design for GSPS ADCs

Design files

TIDA-00359

Design files

Overview

Low cost, high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765, a low noise frequency synthesizer, generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and SFDR performance.

Features
  • Frequency ranges from 300MHz to 4.8GHz
  • Low noise VCO ~ 133dBc/Hz
  • Low jitter: 0.35ps
  • This reference design is tested and includes an evaluation board, configuration software and User's Guide
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Design files & products

Design files

Download ready-to-use system files to speed your design process.

download Design guide — TIDA-00359
TIDU829.PDF (374 KB)

Reference design overview and verified performance test data

download Assembly drawing — TIDA-00359
TIDRD90.PDF (1262 KB)

Detailed overview of design layout for component placement

download Bill of materials (BOM) — TIDA-00359
TIDRD89.PDF (62 KB)

Complete listing of design components, reference designators, and manufacturers/part numbers

download CAD/CAE symbol — TIDA-00359
TIDRD92.ZIP (10461 KB)

Files used for 3D models or 2D drawings of IC components

download CAD/CAE symbol — TIDA-00359
TIDRD93.ZIP (3548 KB)

Files used for 3D models or 2D drawings of IC components

download PCB layout — TIDA-00359
TIDRD91.PDF (6792 KB)

PCB layer plot file used for generating PCB design layout

download Schematic — TIDA-00359
TIDRD88.PDF (1278 KB)

Detailed schematic diagram for design layout and components

Products

Includes TI products in the design and potential alternatives.

RF PLLs & synthesizers

TRF3765 — 300M-4800MHz Low Noise Integer-N/Fractional-N PLL with Integrated VCO and up to 8 Outputs

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS74901 — 3-A, low-VIN (0.8-V) adjustable ultra-low-dropout voltage regulator with power good and enable

Data sheet: PDF | HTML
Clock jitter cleaners

LMK04828 — Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Data sheet: PDF | HTML
High-speed ADCs (≥10 MSPS)

ADC12J4000 — 12-Bit, 4.0-GSPS, RF Sampling Analog-to-Digital Converter (ADC)

Data sheet: PDF | HTML
DC/DC converters

TPS54327 — 4.5V to 18V Input, 3-A Synchronous Step-Down Converter

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

LP38513 — 3-A, ultra-low-dropout voltage regulator with power good & enable for 1.8 V

Data sheet: PDF | HTML
Voltage translators

SN74AVC4T774 — Four-bit dual-supply bus transceiver with configurable voltage-level shifting and tri-state outputs

Data sheet: PDF | HTML

Start development

Hardware development

Evaluation board

ADC12J4000EVM — ADC12J4000 12-Bit, 4.0-GSPS, RF Sampling Analog-to-Digital Converter Evaluation Module

Low cost, high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765, a low noise frequency synthesizer, generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and (...)

EVM user’s guide: PDF
Supported products & hardware

Supported products & hardware

Hardware development
Reference design
TIDA-00359 — Clocking Solution Reference Design for GSPS ADCs
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ADC12J4000EVM — ADC12J4000 12-Bit, 4.0-GSPS, RF Sampling Analog-to-Digital Converter Evaluation Module

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Hardware development
Reference design
TIDA-00359 — Clocking Solution Reference Design for GSPS ADCs
TI’s Standard Terms and Conditions for Evaluation Items apply.

Technical documentation

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Top documentation Type Title Format options Date
* Design guide Clock Solution for GSPS ADCs Design Guide Mar 6, 2015
User guide TIDA-00359 Gerber Mar 6, 2015

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