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ADC12J4000EVM

ADC12J4000 12-Bit, 4.0-GSPS, RF Sampling Analog-to-Digital Converter Evaluation Module

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ADC12J4000EVM

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Overview

The ADC12J4000EVM is an evaluation module (EVM) that allows for the evaluation of TI's ADC12J4000. The ADC12J4000 is a low power, 12-bit, 4-GSPS RF-sampling analog to digital converter (ADC) with a buffered analog input, integrated Digital Down Converter with programmable NCO and decimation settings (including un-decimated 12 bit ADC output) and features a JESD204B interface. The EVM has a transformer coupled analog input to accommodate a wide range of signal sources and frequencies. An LMX2581 clock synthesizer and LMK04828 JESD204B clock generator are included on the EVM and can be configured to provide an ultra-low-jitter ADC Device Clock and SYSREF for a complete JESD204B subclass 1 clocking solution.

The ADC12J4000, LMX2581 and LMK04828 are controlled through an easy to use software GUI to enable quick configuration for a variety of uses.

The ADC12J4000EVM connects directly to the TSW14J56EVM data capture hardware via the high speed FMC connector.  The High Speed Data Converter Pro Software is also available for data capture and analysis support when using the TSW14J56EVM.

Features
  • Flexible transformer coupled analog input and clock input to allow for a variety of sources and frequencies
  • Easy to use software GUI to configure the ADC12J4000, LMX2581 and LMK04828 for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High Speed Data Converter Pro software
  • Simple connection to TSW14J56EVM data capture card
High-speed ADCs (>10MSPS)
ADC12J4000 — 12-Bit, 4.0-GSPS, RF Sampling Analog-to-Digital Converter (ADC)

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Evaluation board

ADC12J4000EVM – ADC12J4000 Evaluation Module

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Technical documentation

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Type Title Date
* User guide ADC12Jxx00 Design Package - Board rev A (Rev. A) Aug. 06, 2015
* User guide ADC12J4000EVM User's Guide (Rev. B) Jul. 27, 2015
Certificate ADC12J4000EVM EU Declaration of Conformity (DoC) Jan. 02, 2019
Application note Extending JESD204B Link Distance on Low-Cost Substrates Dec. 22, 2015
Technical article JESD204B: Serial link quality tradeoffs and tools for optimization Mar. 20, 2015
Technical article JESD204B: Determining your link configuration Sep. 24, 2014

Related design resources

Hardware development

EVALUATION BOARD
TSW14J50EVM — Data capture/pattern generator: data converter EVM with 8 JESD204B lanes from 0.6-6.5Gbps TSW14J56EVM — Data capture/pattern generator: data converter EVM with 8 JESD204B lanes from 0.6-12.5Gbps TSW14J57EVM — Data capture/pattern generator: data converter EVM with 16 JESD204B lanes from 1.6-15Gbps
INTERFACE ADAPTER
TSW14J10EVM — Data Converter Evaluation Module to FPGA Platform FMC Adapter: 10 JESD204B Lanes up to 12.5Gbps

Software development

SUPPORT SOFTWARE
DATACONVERTERPRO-SW — High-speed data converter pro software

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