The ADC12J4000EVM is an evaluation module (EVM) that allows for the evaluation of TI's ADC12J4000. The ADC12J4000 is a low power, 12-bit, 4-GSPS RF-sampling analog to digital converter (ADC) with a buffered analog input, integrated Digital Down Converter with programmable NCO and decimation settings (including un-decimated 12 bit ADC output) and features a JESD204B interface. The EVM has a transformer coupled analog input to accommodate a wide range of signal sources and frequencies. An LMX2581 clock synthesizer and LMK04828 JESD204B clock generator are included on the EVM and can be configured to provide an ultra-low-jitter ADC Device Clock and SYSREF for a complete JESD204B subclass 1 clocking solution.
The ADC12J4000, LMX2581 and LMK04828 are controlled through an easy to use software GUI to enable quick configuration for a variety of uses.
The ADC12J4000EVM connects directly to the TSW14J56EVM data capture hardware via the high speed FMC connector. The High Speed Data Converter Pro Software is also available for data capture and analysis support when using the TSW14J56EVM.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | User guide | ADC12Jxx00 Design Package - Board rev A (Rev. A) | 06 Aug 2015 | |
| * | EVM User's guide | ADC12J4000EVM User's Guide (Rev. B) | 27 Jul 2015 | |
| Certificate | ADC12J4000EVM EU Declaration of Conformity (DoC) | 02 Jan 2019 | ||
| Application note | Extending JESD204B Link Distance on Low-Cost Substrates | 22 Dec 2015 | ||
| Technical article | JESD204B: Serial link quality tradeoffs and tools for optimization | 20 Mar 2015 | ||
| Technical article | JESD204B: Determining your link configuration | 24 Sep 2014 |
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