JAJU446A December   2017  – January 2022

 

  1.   概要
  2.   Resources
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1 System Description
    1. 1.1 Key System Specifications
  7. 2 System Overview
    1. 2.1 Block Diagram
    2. 2.2 System-Level Description
    3. 2.3 Highlighted Products
      1. 2.3.1 Analog Signal Chain
        1. 2.3.1.1 LMH5401
        2. 2.3.1.2 LHM6401
        3. 2.3.1.3 BUF802
      2. 2.3.2 Clock
        1. 2.3.2.1 LMK61E2
        2. 2.3.2.2 LMK04828
        3. 2.3.2.3 LMX2594
      3. 2.3.3 Power
        1. 2.3.3.1 TPS82130
        2. 2.3.3.2 TPS7A84
    4. 2.4 System Design Theory
      1. 2.4.1 High-Speed, Low-Phase Noise Clock Generation
      2. 2.4.2 Channel-to-Channel Skew
      3. 2.4.3 Deterministic Latency
        1. 2.4.3.1 Importance of Deterministic Latency
      4. 2.4.4 Analog Front End
      5. 2.4.5 Multichannel System Power Requirement
      6. 2.4.6 Hardware Programming
  8. 3 Circuit Design
    1. 3.1 Analog Input Front End
      1. 3.1.1 High-Input Impedance Buffer Implementation Using the BUF802
    2. 3.2 High-Speed Multichannel Clocking
    3. 3.3 Power Supply Section
      1. 3.3.1 DC-DC
        1. 3.3.1.1 How to Set 2.1-V Output Voltage
      2. 3.3.2 LDOs
  9. 4 Host Interface
  10. 5 Hardware Functional Block
  11. 6 Getting Started Application GUI
  12. 7 Testing and Results
    1. 7.1 Test Setup and Test Plan
    2.     44
    3. 7.2 SNR Measurement Test
    4. 7.3 Channel-to-Channel Skew Measurement Test
    5. 7.4 Performance Test Result
    6. 7.5 Multichannel Skew Measurement
    7. 7.6 49
  13. 8 Design Files
    1. 8.1 Schematics
    2. 8.2 Bill of Materials
    3. 8.3 Altium Project
    4. 8.4 Gerber Files
    5. 8.5 Assembly Drawings
  14. 9 Software Files
  15. 10Related Documentation
    1. 10.1 Trademarks
  16. 11About the Authors
    1. 11.1 Acknowledgment
  17. 12Revision History

3.3.2 LDOs

The TPS7A8400 is a positive-voltage (5-V), ultra-low-noise (4.4-μVRMS) LDO capable of sourcing a 3-A load with a low drop of 180 mV (see Figure 3-12). The TPS7A8x00 is designed primarily for high-accuracy, high-precision instrumentation applications where clean voltage rails are critical to maximize system performance. This feature makes the device ideal for powering operational amplifiers (op amps), ADCs, DACs, and other high-performance analog circuitry.

The TPS7A8400 has ANY-OUT™ programmable pins to program the desired output voltage. The sum of the internal reference voltage (VREF = 0.8 V) plus the accumulated sum of the respective voltage is assigned to each active pin. The ANY-OUT pins (pins 10, 7, and 6) are programmed to active low to obtain 1.9 V at the output. Other positive rails (1.1 V, 3.3 V, and 2.5 V) are similarly generated.

GUID-0D7D0348-15AE-4F57-A90A-BBF6B7924C91-low.gifFigure 3-12 LDO Power Supply Circuit (1.9-V Rail)

The TPS7A33 series of linear regulators are negative voltage (–36 V), ultra-low-noise (16-µVRMS, 72-dB power supply rejection ratio (PSRR)) linear regulators capable of sourcing a maximum load of 1 A. The output set resistors generate the –2.5 V.