JAJU446A December 2017 – January 2022
Evaluate the design system performance using TI’s TSW14J56 JESD204B high-speed data capture and pattern generator card. Using Altera FPGA JESD204B intellectual property (IP) cores, the TSW14J56 is dynamically configurable to support lane speeds from 600 Mbps to 12.5 Gbps, from one to eight lanes, 1 to 16 converters, and 1 to 4 octets per frame with one firmware build. Together with the accompanying HSDC Pro GUI, the TSW14J56 is a complete system that captures and evaluates data samples from the TIDA-01022 design. The TIDA-01022 design can interface with the TSW14J56 EVM by using an FMC+ to FMC adapter PCB.
For more information on the TSW14J56 EVM, see TSW14J56 JESD204B High-Speed Data Capture/ Pattern Generator Card User's Guide.