JAJU446A December   2017  – January 2022

 

  1.   概要
  2.   Resources
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1 System Description
    1. 1.1 Key System Specifications
  7. 2 System Overview
    1. 2.1 Block Diagram
    2. 2.2 System-Level Description
    3. 2.3 Highlighted Products
      1. 2.3.1 Analog Signal Chain
        1. 2.3.1.1 LMH5401
        2. 2.3.1.2 LHM6401
        3. 2.3.1.3 BUF802
      2. 2.3.2 Clock
        1. 2.3.2.1 LMK61E2
        2. 2.3.2.2 LMK04828
        3. 2.3.2.3 LMX2594
      3. 2.3.3 Power
        1. 2.3.3.1 TPS82130
        2. 2.3.3.2 TPS7A84
    4. 2.4 System Design Theory
      1. 2.4.1 High-Speed, Low-Phase Noise Clock Generation
      2. 2.4.2 Channel-to-Channel Skew
      3. 2.4.3 Deterministic Latency
        1. 2.4.3.1 Importance of Deterministic Latency
      4. 2.4.4 Analog Front End
      5. 2.4.5 Multichannel System Power Requirement
      6. 2.4.6 Hardware Programming
  8. 3 Circuit Design
    1. 3.1 Analog Input Front End
      1. 3.1.1 High-Input Impedance Buffer Implementation Using the BUF802
    2. 3.2 High-Speed Multichannel Clocking
    3. 3.3 Power Supply Section
      1. 3.3.1 DC-DC
        1. 3.3.1.1 How to Set 2.1-V Output Voltage
      2. 3.3.2 LDOs
  9. 4 Host Interface
  10. 5 Hardware Functional Block
  11. 6 Getting Started Application GUI
  12. 7 Testing and Results
    1. 7.1 Test Setup and Test Plan
    2.     44
    3. 7.2 SNR Measurement Test
    4. 7.3 Channel-to-Channel Skew Measurement Test
    5. 7.4 Performance Test Result
    6. 7.5 Multichannel Skew Measurement
    7. 7.6 49
  13. 8 Design Files
    1. 8.1 Schematics
    2. 8.2 Bill of Materials
    3. 8.3 Altium Project
    4. 8.4 Gerber Files
    5. 8.5 Assembly Drawings
  14. 9 Software Files
  15. 10Related Documentation
    1. 10.1 Trademarks
  16. 11About the Authors
    1. 11.1 Acknowledgment
  17. 12Revision History

2.4.2 Channel-to-Channel Skew

The delay (channel-to-channel skew) or phase relationship between channels is a very important specification for high-speed multichannel acquisitions. The sample clock delay includes delay lines, data path delay, and ADC aperture delay. An accurate sampling across channels with a sub-picosecond delay presents design challenges. Use an acquired signal as a time reference to measure the sample clock delay. Extract the timing information through fast-Fourier transform (FFT) by using the MathLab program. Adjust this information in any one of the clock chain path components (clock generation, distribution path, and receiver end) or a combination of them.

The ADC12DJ3200 offers noiseless aperture delay adjustment (tAD adjust) features to shift the sampling instance of the ADC in precise steps to synchronize multiple ADC12DJ3200 devices or to fine-tune system latency and channel-to-channel skew.

This reference design uses the ADC tAD to match channel-to-channel delays less than 5 ps. See Section 7.3 for the test setup to measure the channel-to-channel skew of the TIDA-01022 design. The designer can also use the LMX2594 device to meet the delay requirement in sub nanoseconds depending on the system requirements and the delay adjustment features available in the LMK4828 device.