JAJU446A December 2017 – January 2022
The objective of this reference design is to demonstrate a multichannel analog front end (AFE) with a pin-compatible analog-to-digital-converter (ADC) family for different sampling rates requirements. The system signal-to-noise ratio (SNR) measures the AFE performance, which is then compared with the onboard passive balun and active balun and an LMH5401 fully differential amplifier (FDA) with an LMH6401 programmable variable gain amplifier (PVGA). The onboard, complete multichannel clocking solution is designed based on TI high-performance clocking parts LMK61E2, LMK4828, and LMX2594. Table 1-1 lists the key system-level specifications from the AFE with a multichannel clocking perspective.
Multichannel, high-speed, giga-sample acquisition applications such as a digital storage oscilloscope (DSO), phased-array radio detection and ranging (RADAR), multiple-input multiple-output (MIMO) for wireless communication, and 5G wireless testers all require accurate phase coherence between channels for accurate data acquisition with a high-input signal bandwidth.
Most high-speed digitizers (DSOs) feature only a few channels. Synchronizing the sample clock in a multichannel system is necessary in applications that require tens or hundreds of channels and time correlation between these channels. Clock synchronization in a system with just a few channels is very challenging in and of itself and even more complex when working with an increased channel count.