JAJU446A December   2017  – January 2022

 

  1.   概要
  2.   Resources
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1 System Description
    1. 1.1 Key System Specifications
  7. 2 System Overview
    1. 2.1 Block Diagram
    2. 2.2 System-Level Description
    3. 2.3 Highlighted Products
      1. 2.3.1 Analog Signal Chain
        1. 2.3.1.1 LMH5401
        2. 2.3.1.2 LHM6401
        3. 2.3.1.3 BUF802
      2. 2.3.2 Clock
        1. 2.3.2.1 LMK61E2
        2. 2.3.2.2 LMK04828
        3. 2.3.2.3 LMX2594
      3. 2.3.3 Power
        1. 2.3.3.1 TPS82130
        2. 2.3.3.2 TPS7A84
    4. 2.4 System Design Theory
      1. 2.4.1 High-Speed, Low-Phase Noise Clock Generation
      2. 2.4.2 Channel-to-Channel Skew
      3. 2.4.3 Deterministic Latency
        1. 2.4.3.1 Importance of Deterministic Latency
      4. 2.4.4 Analog Front End
      5. 2.4.5 Multichannel System Power Requirement
      6. 2.4.6 Hardware Programming
  8. 3 Circuit Design
    1. 3.1 Analog Input Front End
      1. 3.1.1 High-Input Impedance Buffer Implementation Using the BUF802
    2. 3.2 High-Speed Multichannel Clocking
    3. 3.3 Power Supply Section
      1. 3.3.1 DC-DC
        1. 3.3.1.1 How to Set 2.1-V Output Voltage
      2. 3.3.2 LDOs
  9. 4 Host Interface
  10. 5 Hardware Functional Block
  11. 6 Getting Started Application GUI
  12. 7 Testing and Results
    1. 7.1 Test Setup and Test Plan
    2.     44
    3. 7.2 SNR Measurement Test
    4. 7.3 Channel-to-Channel Skew Measurement Test
    5. 7.4 Performance Test Result
    6. 7.5 Multichannel Skew Measurement
    7. 7.6 49
  13. 8 Design Files
    1. 8.1 Schematics
    2. 8.2 Bill of Materials
    3. 8.3 Altium Project
    4. 8.4 Gerber Files
    5. 8.5 Assembly Drawings
  14. 9 Software Files
  15. 10Related Documentation
    1. 10.1 Trademarks
  16. 11About the Authors
    1. 11.1 Acknowledgment
  17. 12Revision History

2.2 System-Level Description

Figure 2-2, Figure 2-3, and Figure 2-4 show the subsystem block diagrams of the high-performance DSO, phase-array RADAR, and wireless tester, respectively. The AFE and system clocking architecture are highlighted in each diagram and are common across all three pieces of end equipment.

GUID-579EE2E2-7129-44BF-9068-AD6B55A1360A-low.gifFigure 2-2 High-Performance DSO AFE Subsystem
GUID-B1271B68-06F2-41A3-A2A6-3D49C83CD6B7-low.gifFigure 2-3 RADAR RF Front-End Subsystem
GUID-BAD5D731-1185-4C99-94BA-EDD86F0B7BBA-low.gifFigure 2-4 Wireless Tester AFE Subsystem

High-performance, multichannel digital storage oscilloscopes require a signal chain with a wideband AFE, high dynamic range, high SNR, and low channel-to-channel skew. The analog bandwidth is in the order of a 200-MHz to 5-GHz range and the sampling rate requires 5 Gsps to 10 Gsps.

Wireless testers require high dynamic range and wideband receivers to test 5G and later standards for wireless compliant equipment. These testers require a new high-performance DAC and ADC to obtain the true performance for high accuracy. The requirement of higher data capacity and user data demands a higher carrier frequency compared to the cellular implementation below 6 GHz of today. At the time of this writing, the final specifications for the 5G standard is not available; however, a bandwidth around 500 MHz to 2 GHz is currently under consideration.

Phased-array radar applications require a high dynamic range, wide receiver bandwidth, low latency, and good synchronization between the channels. This reference design front end covers the RADAR lower-band range from 0.3 GHz to 4 GHz (UHF, L band, and S band).