This reference design focuses on design of an analog front end with 50-Ω input as previously discussed, however in some use cases like that of DSO it is often desired to have a capability of a high-input impedance input to the tune of 1 MΩ. BUF802 helps implement this requirement by use of a JFET input unity gain buffer.

Data acquisition systems that require a high-input impedance mode usually follow one of two approaches; a custom front-end ASIC or a discrete JFET implementation. Either of these approaches incur either a high cost of developing and manufacturing a custom ASIC or a complex discrete circuit that comes with its own set of design challenges. The BUF802 provides a single chip alternative to both ASIC and FET-based implementations by providing an all-in-one solution that provides a simpler and more cost-effective solution without sacrificing performance.

The typical discrete implementation, Figure 3-2, uses a precision amplifier and a discrete JFET configured in a composite loop. The purpose of the composite loop architecture is to split the input signal into low- and high-frequency signal paths, pushing through two different circuits and recombining them at the output. One of the main challenges with the composite loop architecture shown in Figure 3-3 is achieving smooth interleaving of the two paths to ensure a flat frequency response. Any mismatch in the transfer function of the two paths leads to discontinuity in the net transfer function frequency response resulting in a loss of signal fidelity, see Figure 3-3.

Additional drawbacks with implementing a discrete design include, but are not limited to: dealing with a complex system response, higher supply rails, component and channel mismatch, additional compensating for input and output protection. For a more in-depth look on discrete design challenges and how the BUF802 helps overcome these problems, see the Simplify analog front-end designs with Hi-Z buffersE2E™ forum.

Figure 3-4 shows the TIDA-01022 fully differential AFE that is configured for a 1.5-GHz BW (bandwidth) application and a 50-Ω input impedance. In the default configuration the AFE cannot be used to achieve high-Z mode for lower frequencies. By implementing the BUF802 composite loop at the beginning of the AFE signal chain, the functionality of a high-input impedance mode can be added.

Figure 3-5 features a 1-GHz front-end design incorporating the BUF802 to the existing reference design. Adding the BUF802 into the signal chain provides the system with a high input impedance of 50 GΩ || 2.4 pF, while maintaining the performance of the original design up to 1 GHz. The ability to switch between high-Z and 50-Ω impedance mode is achieved with a switch or relay at the input.

Using the BUF802 EVM and the TIDA-01022 hardware, the performance of the signal chain with and without the BUF802 can be measured. Figure 3-6 through Figure 3-8 show different performance metrics.