SLASFA2B November   2024  – October 2025 MSPM0G1518 , MSPM0G1519 , MSPM0G3518 , MSPM0G3519

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Device Comparison Chart
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
    3. 6.3 Signal Descriptions
      1.      13
      2.      14
      3.      15
      4.      16
      5.      17
      6.      18
      7.      19
      8.      20
      9.      21
      10.      22
      11.      23
      12.      24
      13.      25
      14.      26
      15.      27
      16.      28
      17.      29
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
      2. 7.6.2 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 Comparator (COMP)
      1. 7.15.1 Comparator Electrical Characteristics
    16. 7.16 DAC
      1. 7.16.1 DAC_Supply Specifications
      2. 7.16.2 DAC Output Specifications
      3. 7.16.3 DAC Dynamic Specifications
      4. 7.16.4 DAC Linearity Specifications
      5. 7.16.5 DAC Timing Specifications
    17. 7.17 I2C
      1. 7.17.1 I2C Characteristics
      2. 7.17.2 I2C Filter
      3. 7.17.3 I2C Timing Diagram
    18. 7.18 SPI
      1. 7.18.1 SPI
      2. 7.18.2 SPI Timing Diagram
    19. 7.19 UART
    20. 7.20 TIMx
    21. 7.21 TRNG
      1. 7.21.1 TRNG Electrical Characteristics
      2. 7.21.2 TRNG Switching Characteristics
    22. 7.22 Emulation and Debug
      1. 7.22.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Functional Block Diagram
    2. 8.2  CPU
    3. 8.3  Operating Modes
      1. 8.3.1 Functionality by Operating Mode (MSPM0Gx51x)
    4. 8.4  Power Management Unit (PMU)
    5. 8.5  Clock Module (CKM)
    6. 8.6  DMA
    7. 8.7  Events
    8. 8.8  Memory
      1. 8.8.1 Memory Organization
      2. 8.8.2 Peripheral File Map
      3. 8.8.3 Peripheral Interrupt Vector
    9. 8.9  Flash Memory
    10. 8.10 SRAM
    11. 8.11 GPIO
    12. 8.12 IOMUX
    13. 8.13 ADC
    14. 8.14 Temperature Sensor
    15. 8.15 VREF
    16. 8.16 COMP
    17. 8.17 DAC
    18. 8.18 Security
    19. 8.19 TRNG
    20. 8.20 AESADV
    21. 8.21 Keystore
    22. 8.22 CRC-P
    23. 8.23 MATHACL
    24. 8.24 UART
    25. 8.25 I2C
    26. 8.26 SPI
    27. 8.27 CAN-FD
    28. 8.28 Low-Frequency Sub System (LFSS)
    29. 8.29 RTC_B
    30. 8.30 IWDT_B
    31. 8.31 WWDT
    32. 8.32 Timers (TIMx)
    33. 8.33 Device Analog Connections
    34. 8.34 Input/Output Diagrams
    35. 8.35 Serial Wire Debug Interface
    36. 8.36 Boot Strap Loader (BSL)
    37. 8.37 Device Factory Constants
    38. 8.38 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tray Information
    2.     PACKAGE OPTION ADDENDUM

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZAW|100
  • PM|64
  • RGZ|48
  • RHB|32
  • PN|80
  • PZ|100
  • PT|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 Functionality by Operating Mode (MSPM0Gx51x)

Supported functionality in each operating mode is given in Table 8-1.

Functional key:

  • EN: The function is enabled in the specified mode.
  • DIS: The function is disabled (either clock or power gated) in the specified mode, but the function's configuration is retained.
  • OPT: The function is optional in the specified mode, and remains enabled if configured to be enabled.
  • NS: The function is not automatically disabled in the specified mode, but it is not supported.
  • OFF: The function is fully powered off in the specified mode, and no configuration information is retained. When waking up from an OFF state, all module registers must be re-configured to the desired settings by application software.

Table 8-1 Supported Functionality by Operating Mode
OPERATING MODERUNSLEEPSTOPSTANDBYSHUTDOWN
RUN0RUN1RUN2SLEEP0SLEEP1SLEEP2STOP0STOP1STOP2STANDBY0STANDBY1
OscillatorsSYSOSCENDISENDISOPT(1)ENDISDISOFF
LFOSC or LFXTEN (LFOSC or LFXT)OFF
HFXTOPTDISOPTDISDISDISOFF
SYSPLLOPTDIS(4)OPTDIS(4)DIS(4)DIS(4)OFF
ClocksCPUCLK80 MHz32 kHzDISOFF
MCLK to PD180 MHz32 kHz80 MHz32 kHzDISOFF
ULPCLK to PD040 MHz32 kHz40 MHz32 kHz4 MHz(1)4 MHz32 kHz32 kHzDISOFF
ULPCLK to TIMG0/8/9/1440 MHz32 kHz40 MHz32 kHz4 MHz(1)4 MHz32 kHz32 kHz32 kHz(2)OFF
RTCCLK32 kHzOFF
MFCLKOPTDISOPTDISOPTDISDISOFF
MFPCLKOPTDISOPTDISOPTDISDISOFF
LFCLK to PD0/132 kHzDISOFF
LFCLK to TIMG0/8/9/1432 kHz32 kHz(2)OFF
LFCLK MonitorOPTOFF
MCLK MonitorOPTDISOFF
PMUPOR monitorEN
BOR monitorENOFF
Core regulatorFULL DRIVEREDUCED DRIVELOW DRIVEOFF
Core FunctionsCPUENDISOFF
DMAOPTDIS (triggers supported)OFF
FlashENDISOFF
SRAM (B0)ENDISOFF
SRAM (B1)OPTDIS / OFFOFFOFF
PD1 PeripheralsMATHACLOPTOFFOFF
UART3/4/5/6OPTDISOFF
SPI0/1/2OPT

DIS

OFF
MCAN0/1OPTOFFOPTOFFOFFOFF
TIMA0/1OPTOFFOFF
TIMG6/7/12OPTOFFOFF
AESADVOPTOFFOFF
CRC-POPTDISOFF
TRNGOPTOFFOFF
PD0 PeripheralsGPIOA/B/C(3)OPTOPT(2)OFF
UART0/1/7OPTOPT(2)OFF
I2C0/1/2OPTOPT(2)OFF
TIMG0/8/9/14OPTOPT(2)OFF
WWDT0/1OPTDISOFF
IWDTOPTOFF
RTC_BOPTOFF
KeystoreOPTOFF
AnalogVREFOPTOFF
ADC0/1(3)OPTNS (triggers supported)OFF
COMP0/1/2OPTOPT (ULP)OPTOPT (ULP)OPTOPT (ULP)OFF
DAC0OPTNSOFF

Temperature Sensor

OPTOFFOFF
IOMUX and IO WakeupENDIS w/ WAKE
Wake SourcesN/AANY IRQPD0 IRQIOMUX, NRST, SWD
(1) If STOP0 is entered from RUN1 (SYSOSC enabled but MCLK sourced from LFCLK), SYSOSC remains enabled as it was in RUN1, and ULPCLK remains at 32 kHz as it was in RUN1. If STOP0 is entered from RUN2 (SYSOSC was disabled and MCLK was sourced from LFCLK), SYSOSC remains disabled as it was in RUN2, and ULPCLK remains at 32 kHz as it was in RUN2.
(2) When using the STANDBY1 policy for STANDBY, only specific peripherals (TIMG0, TIMG8, TIMG9, TIMG14, and RTC) are clocked. Other PD0 peripherals can generate an asynchronous fast clock request upon external activity but are not actively clocked.
(3) For ADCx and GPIOx Ports, the digital logic is in PD0 and the register interface is in PD1. These peripherals support fast single-cycle register access when PD1 is active and also support basic operation down to STANDBY mode where PD0 is still active.
(4) SYSPLL is not automatically disabled, and needs to be manually disabled through the HSCLKEN.SYSPLLEN field within the SYSCTL registers in order to reduce power consumption.